公开(公告)号：US20110119566A1

公开(公告)日：2011-05-19

申请号：US13007004

申请日：2011-01-14

申请人： Nils Graef ,  Zachary Keirn

发明人： Nils Graef ,  Zachary Keirn

IPC分类号： H03M13/45 ,  G06F11/10 ,  H03M13/41

CPC分类号： H03M13/47 ,  H03M13/3905 ,  H03M13/4146 ,  H03M13/612

摘要： Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

摘要翻译： 提供了用于测量读取通道的性能的方法和装置。 诸如SOVA和最大后验（MAP）检测器的多种检测技术产生与比特决定相关联的比特决策和相应的可靠性值。 与比特决定相关联的可靠性值可以例如以对数似然比（LLR）的形式表示。 可靠性值可以被监视并用作性能测量。 本发明提供了通常与BER直接相关的信道性能测量，但可以在较少的时间内收集。

公开(公告)号：US07941732B2

公开(公告)日：2011-05-10

申请号：US12750049

申请日：2010-03-30

申请人： Nils Graef ,  Zachary Keirn

发明人： Nils Graef ,  Zachary Keirn

IPC分类号： H03M13/00

CPC分类号： H03M13/47 ,  H03M13/3905 ,  H03M13/4146 ,  H03M13/612

摘要： Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

公开(公告)号：US20110060894A1

公开(公告)日：2011-03-10

申请号：US12447716

申请日：2008-03-27

申请人： Nils Graef

发明人： Nils Graef

IPC分类号： G06F9/30

CPC分类号： G11B20/10527 ,  G06F1/3221 ,  G06F1/3287 ,  G11B20/10037 ,  G11B2020/10759 ,  G11B2220/2516 ,  Y02D10/154 ,  Y02D10/171

摘要： A processor circuit having reduced power consumption includes an analog front end operative to receive an analog signal supplied to the processor circuit and to generate a digital signal indicative of the analog signal. The processor further includes a digital back end operative to generate a digital output signal as a function of the digital signal generated by the analog front end. A buffer is coupled between the analog front end and the digital back end. In a first mode of operation, the digital hack end operates at a substantially same data rate as the analog front end and the buffer is bypassed. In a second mode of operation, the digital back end operates at a higher data rate than the analog front end and the buffer is used to store outputs of the analog front end.

摘要翻译： 具有降低的功耗的处理器电路包括模拟前端，其操作以接收提供给处理器电路的模拟信号并产生指示模拟信号的数字信号。 处理器还包括数字后端，用于根据由模拟前端产生的数字信号产生数字输出信号。 缓冲器耦合在模拟前端和数字后端之间。 在第一操作模式下，数字黑客端以与模拟前端基本相同的数据速率工作，并且旁路缓冲器。 在第二种操作模式下，数字后端以比模拟前端更高的数据速率工作，缓冲器用于存储模拟前端的输出。

公开(公告)号：US07876847B2

公开(公告)日：2011-01-25

申请号：US11085026

申请日：2005-03-16

申请人： Nils Graef ,  Joachim S. Hammerschmidt

发明人： Nils Graef ,  Joachim S. Hammerschmidt

IPC分类号： H04L23/02

CPC分类号： H04L1/06 ,  H04L5/023

摘要： A method for generating soft bit values for a multi-bit symbol encoded in one or more received signals comprises (a) for a plurality of different combinations of multiple bit values, iteratively generating, for each combination, a metric value based on the one or more received signals. The method further comprises (b) for each iteration, maintaining (i) a global extremum register containing a global extremum of the metric values; (ii) a bit occupancy for the global extremum register; and (iii) a plurality of bit bk registers, one for each bit bk in the symbol. Each bit bk register contains an extremum of the metric values corresponding to combinations of multiple bit values whose bit bk value is opposite the bit bk value of the bit occupancy for the global extremum register. The method further comprises (c) generating, for each bit bk in the symbol, a soft bit value based on a difference between the value in the global extremum register and the value in the corresponding bit bk register.

摘要翻译： 一种用于为在一个或多个接收信号中编码的多比特符号产生软比特值的方法包括（a）针对多个比特值的多个不同组合，对于每个组合迭代地生成基于该一个或多个 更多的信号。 该方法还包括（b）对于每次迭代，维持（i）包含度量值的全局极值的全局极值寄存器; （ii）全球极值登记册的位占有率; 和（iii）多个位bk寄存器，一个用于符号中的每个位bk。 每个位bk寄存器包含与位bk值与全局极值寄存器的位占用的位bk值相反的多个位值的组合对应的度量值的极值。 所述方法还包括（c）基于所述全局极值寄存器中的值与对应的位bk寄存器中的值之间的差，为符号中的每个位bk产生软比特值。

公开(公告)号：US07729075B2

公开(公告)日：2010-06-01

申请号：US11982261

申请日：2007-10-31

申请人： Nils Graef

发明人： Nils Graef

IPC分类号： G11B5/09

CPC分类号： G11B5/09

摘要： An improved mass storage system having a read channel adapted to store in a FIFO memory digitized analog samples of data symbols read from a disk, the buffered digitized samples being processed by digital circuitry that may be operated at a slower speed than the maximum symbol rate from the disk. In one embodiment, the read channel has an analog portion that processes analog signals from a read head and includes an ADC for converting the processed analog signals into digital samples in response to a first clock; a FIFO storing therein the digital samples in response to the first clock and reading out the stored digital samples in response to a second clock; and a detector, in response to the second clock, detecting the digital samples from the FIFO into digital data. The maximum frequency of the first clock is less than the maximum frequency of the second clock.

摘要翻译： 一种改进的大容量存储系统，其具有适于存储在FIFO存储器中的数字化的从盘读取的数据符号的模拟采样的读通道，所缓冲的数字化采样由数字电路处理，数字电路可以以比最大符号率 磁盘。 在一个实施例中，读通道具有处理来自读头的模拟信号的模拟部分，并且包括用于响应于第一时钟将经处理的模拟信号转换成数字样本的ADC; FIFO，其响应于第一时钟存储数字样本，并响应于第二时钟读出存储的数字样本; 以及响应于第二时钟的检测器，将来自FIFO的数字样本检测为数字数据。 第一个时钟的最大频率小于第二个时钟的最大频率。

公开(公告)号：US20100131819A1

公开(公告)日：2010-05-27

申请号：US12323626

申请日：2008-11-26

申请人： Nils Graef

发明人： Nils Graef

IPC分类号： H03M13/07 ,  G06F11/10

CPC分类号： H03M13/116 ,  G06F11/1004 ,  H03M13/1117 ,  H03M13/1137 ,  H03M13/658 ,  H03M13/6591

摘要： In one embodiment, the present invention is a variable node unit (VNU) of a low-density parity-check (LDPC) decoder. The VNU receives a soft-input value and wc check node messages, where wc is the column hamming weight of the LDPC code. The VNU generates (i) an extrinsic log-likelihood ratio (LLR) by adding all wc check node messages together; (ii) a hard-decision output by adding the extrinsic LLR to the soft-input value and selecting the sign bit of the resulting sum; and (iii) wc variable node messages. Each variable node message is generated by adding a different set of (wc−1) check node messages to the soft-input value where each set excludes a different check node message. In so doing, VNUs of the present invention may generate variable node messages using fewer adder stages compared to prior-art VNUs such that throughput may be increased over that of prior-art VNUs.

摘要翻译： 在一个实施例中，本发明是低密度奇偶校验（LDPC）解码器的可变节点单元（VNU）。 VNU接收软输入值并检查节点消息，其中wc是LDPC码的列汉明权重。 VNU通过将所有wc校验节点消息加在一起而产生（i）外在对数似然比（LLR）; （ii）通过将外部LLR加到软输入值并选择所得和的符号位的硬判决输出; 和（iii）wc变量节点消息。 通过将不同的一组（wc-1）校验节点消息添加到软输入值来生成每个变量节点消息，其中每个集合排除不同的校验节点消息。 这样做，与现有技术的VNU相比，本发明的VNU可以使用较少的加法器级产生可变节点消息，使得吞吐量可以比现有技术的VNU的吞吐量增加。

公开(公告)号：US07707449B2

公开(公告)日：2010-04-27

申请号：US11394028

申请日：2006-03-29

申请人： Nils Graef

发明人： Nils Graef

IPC分类号： G06F1/00 ,  H04J12/66 ,  G01R31/28

CPC分类号： H03K5/135 ,  H03K3/356104

摘要： Various systems and methods for low power multi-rate data paths are disclosed. As one example, a semiconductor device that includes a multi-rate data path is discussed. The multi-rate data path includes at least two register circuits with an output of one of the register circuits electrically coupled to an input of the other register circuit via a combinational logic block. In addition, the semiconductor device includes a control circuit that is operable to modify the rate at which the multi-rate data path operates by selectably bypassing at least one of the register circuits.

摘要翻译： 公开了用于低功率多速率数据路径的各种系统和方法。 作为一个例子，讨论了包括多速率数据路径的半导体器件。 多速率数据路径包括至少两个寄存器电路，其中一个寄存器电路的输出经由组合逻辑块电耦合到另一寄存器电路的输入。 此外，半导体器件包括控制电路，其可操作以通过可选择地旁路至少一个寄存器电路来修改多速率数据路径操作的速率。

公开(公告)号：US20090199071A1

公开(公告)日：2009-08-06

申请号：US12025924

申请日：2008-02-05

申请人： Nils Graef

发明人： Nils Graef

IPC分类号： H03M13/00 ,  G06F11/00

CPC分类号： H03M13/1137 ,  H03M13/1111 ,  H03M13/6325

摘要： Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various embodiments of the present invention provide LDPC decoder circuits that include a soft-input memory, a memory unit, and an arithmetic unit. The arithmetic unit includes a hardware circuit that is selectably operable to perform a row update and a column update. In such cases, a substantial portion of the circuitry of the hardware circuit used to perform the row update is re-used to perform the column update.

摘要翻译： 本发明的各种实施例提供了提供LDPC解码和/或纠错的系统和电路。 例如，本发明的各种实施例提供了包括软输入存储器，存储器单元和运算单元的LDPC解码器电路。 算术单元包括可选择地可操作地执行行更新和列更新的硬件电路。 在这种情况下，用于执行行更新的硬件电路的大部分电路被重新用于执行列更新。

公开(公告)号：US20090109564A1

公开(公告)日：2009-04-30

申请号：US11982261

申请日：2007-10-31

申请人： Nils Graef

发明人： Nils Graef

IPC分类号： G11B5/09

CPC分类号： G11B5/09

摘要： An improved mass storage system having a read channel adapted to store in a FIFO memory digitized analog samples of data symbols read from a disk, the buffered digitized samples being processed by digital circuitry that may be operated at a slower speed than the maximum symbol rate from the disk. In one embodiment, the read channel has an analog portion that processes analog signals from a read head and includes an ADC for converting the processed analog signals into digital samples in response to a first clock; a FIFO storing therein the digital samples in response to the first clock and reading out the stored digital samples in response to a second clock; and a detector, in response to the second clock, detecting the digital samples from the FIFO into digital data. The maximum frequency of the first clock is less than the maximum frequency of the second clock.

摘要翻译： 一种改进的大容量存储系统，其具有适于存储在FIFO存储器中的数字化的从盘读取的数据符号的模拟采样的读通道，所缓冲的数字化采样由数字电路处理，数字电路可以以比最大符号率 磁盘。 在一个实施例中，读通道具有处理来自读头的模拟信号的模拟部分，并且包括用于响应于第一时钟将经处理的模拟信号转换成数字样本的ADC; FIFO，其响应于第一时钟存储数字样本，并响应于第二时钟读出存储的数字样本; 以及响应于第二时钟的检测器，将来自FIFO的数字样本检测为数字数据。 第一个时钟的最大频率小于第二个时钟的最大频率。

公开(公告)号：US20090030901A1

公开(公告)日：2009-01-29

申请号：US11781364

申请日：2007-07-23

申请人： Nils Graef

发明人： Nils Graef

IPC分类号： G06F17/30

CPC分类号： G06Q30/00

摘要： Various embodiments of the present invention provide systems and methods for responding to business related queries. As one example, such methods may include providing a communication direction associated with a particular business, and receiving a query via the communication direction. The received query is directed to a third party support service where it is parsed and one or more elements of the query are compared against a prior query. A response to the query was previously supplied by the particular business. A response is provided to the query that includes at least a portion of the reply to the prior query.

摘要翻译： 本发明的各种实施例提供用于响应业务相关查询的系统和方法。 作为一个示例，这样的方法可以包括提供与特定业务相关联的通信方向，以及经由通信方向接收查询。 接收到的查询被定向到第三方支持服务，在其中进行解析，并将查询的一个或多个元素与先前的查询进行比较。 以前由特定业务提供对查询的响应。 向查询提供响应，该响应包括对先前查询的答复的至少一部分。