公开(公告)号：US08307203B2

公开(公告)日：2012-11-06

申请号：US12502983

申请日：2009-07-14

Applicant: Charles Fraleigh ,  Nitin Gupta ,  Case Larsen ,  Shashidhar Merugu ,  Eric Ogren ,  Paras Shah ,  Oleg Smolsky

Inventor： Charles Fraleigh ,  Nitin Gupta ,  Case Larsen ,  Shashidhar Merugu ,  Eric Ogren ,  Paras Shah ,  Oleg Smolsky

IPC: H04L29/06

CPC classification number: H04L63/0823 ,  H04L63/166

Abstract: A local network traffic processor and an application are resident on a common computer system. The application is configured to trust a server certificate issued by a local network traffic processor, the local network traffic processor operatively being paired with a remote network traffic processor. A proxy server certificate, generated using identification information of a server associated with the remote network traffic processor and signed by the local certification authority, is used to establish a secure session between a local network traffic processor and the application.

Abstract translation: 本地网络流量处理器和应用程序驻留在通用计算机系统上。 该应用被配置为信任由本地网络流量处理器颁发的服务器证书，本地网络流量处理器可操作地与远程网络流量处理器配对。 使用由与远程网络流量处理器相关联并由本地认证机构签名的服务器的标识信息生成的代理服务器证书来建立本地网络流量处理器和应用之间的安全会话。

公开(公告)号：US20120169393A1

公开(公告)日：2012-07-05

申请号：US12982593

申请日：2010-12-30

Applicant: Nitin Gupta ,  Nitin Jain

Inventor： Nitin Gupta ,  Nitin Jain

IPC: H03K3/356 ,  H03K3/286 ,  H03K3/00

CPC classification number: H03K5/151 ,  H03K2005/00136

Abstract: A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.

Abstract translation: 一种用于处理包括不同极性的第一和第二时钟沿的时钟信号的电路，所述电路包括用于反相第一时钟沿以产生反相第一时钟沿的反相器，并且反相第二时钟沿以产生反相第二时钟沿; 第一通路门，用于接收反相时钟沿并输出第一极性的第一触发信号; 以及第二通路门，用于接收第二时钟沿并输出第一极性的第二触发信号，其中第二通道门被控制为响应于反相的第二时钟沿打开; 由此第一时钟沿和第一触发信号之间的延迟基本上等于第二时钟沿和第二触发信号之间的延迟。

公开(公告)号：US20120161823A1

公开(公告)日：2012-06-28

申请号：US13177956

申请日：2011-07-07

Applicant: Nitin Gupta

Inventor： Nitin Gupta

IPC: H03K21/00

CPC classification number: H03K21/023

Abstract: Circuitry and method for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer. A flip flop is clocked on a first type of edge of the input clock signal, and provides an output for use as a divided clock signal. Feedback circuitry is clocked on the first type of edge of the input clock signal and provides a signal to a data input of the flip flop based on the inverse of the output of the flip flop. In a first mode the feedback circuitry is arranged to allow the signal provided to the data input of the flip flop to follow the inverse of the output of the flip flop so that each first type of edge causes the signal provided to the data input of the flip flop to toggle such that the output of the flip flop has a frequency which is substantially half of the frequency of the input clock signal, and wherein in a second mode the feedback circuitry is arranged to allow the signal provided to the data input of the flip flop to follow the inverse of the output of the flip flop with the exception that toggling of the signal provided to the data input of the flip flop is selectively prevented despite toggling of the output of the flip flop on an edge of the first type such that the output of the flip flop has a frequency which is at most a third of the frequency of the input clock signal. The feedback circuitry is arranged to operate independently from a second type of edge of the input clock signal in providing the signal to the data input of the flip flop, such that the output of the flip flop is independent from the duty cycle of the input clock signal.

Abstract translation: 用于划分用于数字频率合成器的预分频器的输入时钟信号的频率的电路和方法。 触发器在输入时钟信号的第一种类型的边沿上被计时，并提供用作分频时钟信号的输出。 反馈电路在输入时钟信号的第一种类型的边缘上被计时，并且基于触发器的输出的反相将信号提供给触发器的数据输入。 在第一模式中，反馈电路被布置成允许提供给触发器的数据输入的信号跟随触发器的输出的倒数，使得每个第一类型的边缘使得提供给数据输入的信号 触发器进行切换，使得触发器的输出具有基本上是输入时钟信号的频率的一半的频率，并且其中在第二模式中，反馈电路被布置为允许提供给数据输入的信号 触发器遵循触发器的输出的倒数，除了选择性地防止提供给触发器的数据输入的信号的翻转，尽管在第一类型的边缘上触发触发器的输出，例如 触发器的输出具有至多输入时钟信号频率的三分之一的频率。 反馈电路被布置为独立于输入时钟信号的第二类型的边缘操作，以将信号提供给触发器的数据输入，使得触发器的输出独立于输入时钟的占空比 信号。

公开(公告)号：US20120089814A1

公开(公告)日：2012-04-12

申请号：US13310928

申请日：2011-12-05

Applicant: Nitin Gupta ,  Daniel H. Kim ,  Igor Malamant ,  Steve Haehnichen

Inventor： Nitin Gupta ,  Daniel H. Kim ,  Igor Malamant ,  Steve Haehnichen

IPC: G06F15/76 ,  G06F9/06

CPC classification number: G06F9/445 ,  G06F9/06 ,  G06F9/4405

Abstract: In a multiprocessor system, a primary processor may store an executable image for a secondary processor. A communication protocol assists the transfer of an image header and data segment(s) of the executable image from the primary processor to the secondary processor. Messages between the primary processor and secondary processor indicate successful receipt of transferred data, termination of a transfer process, and acknowledgement of same.

Abstract translation: 在多处理器系统中，主处理器可以存储辅助处理器的可执行映像。 通信协议有助于将图像头部和可执行图像的数据段从主处理器传送到次要处理器。 主处理器和辅助处理器之间的消息指示传输数据的成功接收，传送过程的终止以及确认。

公开(公告)号：US20120059713A1

公开(公告)日：2012-03-08

申请号：US13219433

申请日：2011-08-26

Applicant: Daniel Galas ,  Veeravich Thi Thumasathit ,  Murthy V. Nukala ,  Richard Edward Chatwin ,  Alessandro Magnani ,  Benjamin David Foster ,  Alan Coleman ,  Manish Khettry ,  Siva Chandrasekar ,  Nitin Gupta ,  Srinidhi Ramesh Kondaji ,  Venkatesh Natarajan ,  Nitin Duggal

Inventor： Daniel Galas ,  Veeravich Thi Thumasathit ,  Murthy V. Nukala ,  Richard Edward Chatwin ,  Alessandro Magnani ,  Benjamin David Foster ,  Alan Coleman ,  Manish Khettry ,  Siva Chandrasekar ,  Nitin Gupta ,  Srinidhi Ramesh Kondaji ,  Venkatesh Natarajan ,  Nitin Duggal

IPC: G06Q30/02

CPC classification number: G06Q30/0244 ,  G06Q30/0241 ,  G06Q30/0247 ,  G06Q30/0251 ,  G06Q30/0256 ,  G06Q30/0276

Abstract: In one embodiment, a method includes deriving a user intent from user information associated with a user, selecting an advertiser intent that aligns with the user intent, and then advertising to the user based on the advertiser intent that aligns with the user intent.

Abstract translation: 在一个实施例中，一种方法包括从与用户相关联的用户信息中导出用户意图，选择与用户意图一致的广告商意图，然后基于与用户意图一致的广告商意图来广告给用户。

公开(公告)号：US20110090002A1

公开(公告)日：2011-04-21

申请号：US12581578

申请日：2009-10-19

Applicant: Somnath Kundu ,  Pikul Sarkar ,  Nitin Gupta

Inventor： Somnath Kundu ,  Pikul Sarkar ,  Nitin Gupta

IPC: G05F1/10 ,  G11C5/14

CPC classification number: H03K17/00 ,  H03K17/0822

Abstract: An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.

Abstract translation: 集成电路包括多个焊盘。 集成电路还包括具有到第一个焊盘的开漏连接的共源共栅晶体管。 集成电路中包含偏置发生器电路。 偏置发生器电路具有连接到共源共栅晶体管的栅极端子的输出。 在第一操作模式中，偏置发生器输出偏置信号，该偏置信号是从存在于第二焊盘处的集成电路电源电压导出的。 然而，在不存在集成电路电源电压时提供的第二操作模式中，偏置发生器产生从存在于第一焊盘处的电压导出的偏置信号。

公开(公告)号：US20100318665A1

公开(公告)日：2010-12-16

申请号：US12843754

申请日：2010-07-26

Applicant: Michael J. Demmer ,  Kand Ly ,  Nitin Gupta

Inventor： Michael J. Demmer ,  Kand Ly ,  Nitin Gupta

IPC: G06F15/16

CPC classification number: H04L67/14 ,  H04L29/12367 ,  H04L41/12 ,  H04L61/2514 ,  H04L67/2876 ,  H04L69/16 ,  H04L69/163 ,  H04L69/329 ,  H04L69/40

Abstract: Methods and apparatus are provided for intercepting a client-server communication connection in a computing environment. A first network intermediary configured to facilitate optimization of client-server transactions may be installed in a path of communications between the client and the server. A second network intermediary configured to cooperate with the first network intermediary is not in the path of communications between the client and the server. The first network intermediary intercepts a connection request from the client and forwards a modified request toward the server. A module within the server intercepts the connection request and redirects it to the second network intermediary. The client-server connection is thus split-terminated at the two network intermediaries, which establish cooperative sessions between themselves and with the client and with the server.

Abstract translation: 提供了用于在计算环境中拦截客户机 - 服务器通信连接的方法和装置。 配置为促进客户端 - 服务器事务的优化的第一网络中介可以安装在客户机和服务器之间的通信路径中。 配置为与第一网络中介进行协作的第二网络中介不在客户端和服务器之间的通信路径中。 第一个网络中介拦截来自客户端的连接请求，并向服务器转发修改的请求。 服务器内的一个模块拦截连接请求并将其重定向到第二个网络中介。 因此，客户机 - 服务器连接在两个网络中间件上分拆终止，这两个中间件在它们之间以及与客户端和服务器之间建立协作会话。

公开(公告)号：US20100250306A1

公开(公告)日：2010-09-30

申请号：US12569813

申请日：2009-09-29

Applicant: Deepak Sanghi ,  Alok Ashtikar ,  Nitin Gupta ,  Toolika Maria Lewis ,  Sachin Maheshwari ,  Arvindh Murugan

Inventor： Deepak Sanghi ,  Alok Ashtikar ,  Nitin Gupta ,  Toolika Maria Lewis ,  Sachin Maheshwari ,  Arvindh Murugan

IPC: G06Q10/00 ,  G06Q50/00

Abstract: A system and method is disclosed for determining root cause constraints and resolution options to solve order promising exceptions. The system includes a database storing order promise data associated with one or more enterprises. The system further includes a computer coupled with the database, the computer is configured to receive an order promise from the one or more enterprises, define one or more constraints, and create one or more strategy models comprising one or more strategy changes. The computer is further configured to execute the one or more strategy models to relax the one or more constraints using the one or more strategy changes and generate a report of the reasons for lateness and shortness of the order promise and store the generated report in the database.

Abstract translation: 公开了一种用于确定根本原因约束和分辨率选项以解决有序的有希望的例外的系统和方法。 该系统包括存储与一个或多个企业相关联的订单承诺数据的数据库。 该系统还包括与数据库耦合的计算机，该计算机被配置为从一个或多个企业接收订单许可，定义一个或多个约束，以及创建包括一个或多个策略改变的一个或多个策略模型。 计算机还被配置为执行一个或多个策略模型以使用一个或多个策略改变来放松一个或多个约束，并且生成关于订单承诺的延迟和短缺的原因的报告，并将生成的报告存储在数据库中 。

公开(公告)号：US20100241673A1

公开(公告)日：2010-09-23

申请号：US12730185

申请日：2010-03-23

Applicant: David Tze-Si Wu ,  Steven McCanne ,  Michael J. Demmer ,  Nitin Gupta

Inventor： David Tze-Si Wu ,  Steven McCanne ,  Michael J. Demmer ,  Nitin Gupta

IPC: G06F17/30 ,  G06F9/455

Abstract: Virtual storage arrays consolidate branch data storage at data centers connected via wide area networks. Virtual storage arrays appear to storage clients as local data storage; however, virtual storage arrays actually store data at the data center. The virtual storage arrays overcomes bandwidth and latency limitations of the wide area network by predicting and prefetching storage blocks, which are then cached at the branch location. Virtual storage arrays leverage an understanding of the semantics and structure of high-level data structures associated with storage blocks to predict which storage blocks are likely to be requested by a storage client in the near future. Virtual storage arrays determine the association between requested storage blocks and corresponding high-level data structure entities to predict additional high-level data structure entities that are likely to be accessed. From this, the virtual storage array identifies the additional storage blocks for prefetching.

Abstract translation: 虚拟存储阵列将通过广域网连接的数据中心的分支数据存储整合。 虚拟存储阵列对存储客户端显示为本地数据存储; 然而，虚拟存储阵列实际上将数据存储在数据中心。 虚拟存储阵列通过预测和预取存储块来克服广域网的带宽和延迟限制，然后将存储块缓存在分支位置。 虚拟存储阵列利用对与存储块相关联的高级数据结构的语义和结构的理解，以预测存储客户端在不久的将来可能要求哪些存储块。 虚拟存储阵列确定所请求的存储块和相应的高级数据结构实体之间的关联，以预测可能被访问的附加高级数据结构实体。 从此，虚拟存储阵列识别用于预取的附加存储块。

公开(公告)号：US20100228968A1

公开(公告)日：2010-09-09

申请号：US12396904

申请日：2009-03-03

Applicant: Prashant Wason ,  Nitin Gupta ,  Robert Adler

Inventor： Prashant Wason ,  Nitin Gupta ,  Robert Adler

IPC: H04L9/00

CPC classification number: H04L9/3273 ,  H04L9/3263 ,  H04L2209/56

Abstract: A method and apparatus are provided for split-terminating a secure client-server communication connection when the client and server perform mutual authentication by exchanging certificates, such as within a Lotus Notes environment. When the client submits a certificate to the server, an intermediary device intercepts the certificate and submits to the server a substitute client certificate generated by that intermediary. A certificate authority's private key is previously installed on the intermediary to enable it to generate public keys, private keys and digital certificates. With the private key corresponding to the substitute certificate, the intermediary extracts a temporary key from a subsequent server message. The intermediary uses the temporary key to read a session key issued later by the server. Thereafter, the intermediary shares the session key with another intermediary, and together they use the session keys to access and optimize (e.g., accelerate) messages sent by the client and the server.

Abstract translation: 提供了一种方法和装置，用于当客户端和服务器通过交换证书（例如在Lotus Notes环境中）执行相互认证来分离终止安全客户端 - 服务器通信连接。 当客户端向服务器提交证书时，中间设备将截取该证书，并向该服务器提交该中间人产生的替代客户端证书。 证书颁发机构的私钥先前安装在中介上，使其能够生成公钥，私钥和数字证书。 使用对应于替代证书的私钥，中介从后续服务器消息中提取临时密钥。 中间人使用临时密钥来读取稍后由服务器发出的会话密钥。 此后，中间人与另一个中间人共享会话密钥，并且它们一起使用会话密钥来访问和优化（例如，加速）由客户端和服务器发送的消息。