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公开(公告)号：US20180054200A1
公开(公告)日：2018-02-22
申请号：US15679869
申请日：2017-08-17
IPC分类号： H03K19/0185 , H03F3/45 , H03F3/30
CPC分类号： H03F3/45085 , H03F1/0205 , H03F2200/513 , H03K3/012 , H03K3/2885 , H03K21/023
摘要： In accordance with an embodiment, a method includes receiving a first differential logic signal using a first branch of a circuit that extends from a voltage supply of the circuit as far as an earth terminal of the circuit and has at least one first differential transistor pair, receiving a second differential logic signal using a second branch of the circuit that extends from the voltage supply to the earth terminal and has at least one second differential transistor pair, conducting a current flow between the first branch and the second branch, and outputting an output signal by the second branch.
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公开(公告)号：US09797936B2
公开(公告)日：2017-10-24
申请号：US14639432
申请日：2015-03-05
发明人： Adam H. Dewhirst , Chee Fai Yap
CPC分类号： G01R23/02 , G01P3/486 , H03K21/023 , H03K21/40
摘要： An improved counter may implement dynamic frequency measurement while also remaining fully backwards compatible with traditional frequency measurement methods. The counter may operate according to low-frequency, large range, and/or high frequency modes of operation. It may be programmable with a divisor value associated with the large range operating mode, and a measurement time associated with the high frequency mode of operation. The divisor and measurement time settings may be enabled or disabled, and when either setting is disabled, the counter becomes backwards compatible with traditional frequency measurement methods. The counter may also be provided with inputs representative of the desired type of measurement and the minimum and maximum expected values for the signal to be measured. The counter may perform the frequency measurement according to any one or more of the operating modes, and return a measurement result obtained in the operating mode that completes the measurement first.
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公开(公告)号：US09768785B2
公开(公告)日：2017-09-19
申请号：US14850067
申请日：2015-09-10
发明人： Kenneth I. Schultz , Brian Tyrrell , Michael W. Kelly , Curtis B. Colonero , Lawrence M. Candell , Daniel Mooney
CPC分类号： H03K21/023 , G11C19/00 , H03K23/548 , H03M1/001 , H03M1/004 , H03M1/123 , H03M1/60
摘要： Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.
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公开(公告)号：US20170099054A1
公开(公告)日：2017-04-06
申请号：US15380678
申请日：2016-12-15
申请人： SK hynix Inc.
发明人： Won-Seok HWANG
IPC分类号： H03K23/50
CPC分类号： H03K23/50 , H03K21/023
摘要： An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.
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5.发明授权Sensor device with sampling function, and sensor data processing system using same 有权具有采样功能的传感器设备，以及使用该传感器的传感器数据处理系统公开(公告)号：US09534923B2
公开(公告)日：2017-01-03
申请号：US14344617
申请日：2012-02-24
申请人： Masaya Yamashita , Shiro Kobayashi , Osamu Koizumi , Yuko Akagi
发明人： Masaya Yamashita , Shiro Kobayashi , Osamu Koizumi , Yuko Akagi
摘要： The sensor device includes a counter for counting the number of count commands used to perform measurements while maintaining among multiple sensor devices the ratio of measurement intervals; a ratio-holding-unit for setting the ratio to a desired ratio and holding respective values of the ratio for each of the multiple sensor devices; a sampling-timing-generating-unit for receiving a count value of the counter and the setting value of the ratio held by the ratio-holding-unit, and for generating a sampling timing signal based on the comparison result between the count value and the setting value; and a sampling-unit for sampling a detection signal detected by the detecting unit, by using the sampling timing signal generated by the sampling-timing-generating-unit.
摘要翻译： 传感器装置包括用于计数用于执行测量的计数命令的计数器，同时在多个传感器装置之间保持测量间隔的比率; 比例保持单元，用于将所述比率设置为期望比率并保持所述多个传感器装置中的每一个的所述比率的各个值; 采样定时发生单元，用于接收计数器的计数值和由比例保持单元保持的比率的设定值，并且用于基于计数值和计数值之间的比较结果产生采样定时信号 设定值 以及采样单元，用于通过使用由采样定时产生单元产生的采样定时信号对由检测单元检测的检测信号进行采样。
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公开(公告)号：US09531367B2
公开(公告)日：2016-12-27
申请号：US14960425
申请日：2015-12-06
发明人： Ming-Ying Liu
CPC分类号： H03K7/08 , H03K21/023
摘要： A pulse width modulation signal generation circuit and a pulse width modulation signal generation method are provided. A clock generator is configured for generating a clock signal including a plurality of pulses. The counting unit is coupled to the clock generator, and configured for storing a period parameter and outputting a counting value by counting the pulses of the clock signal based on the period parameter and a bidirectional counting mode. The comparing unit is coupled to the counting unit and is configured for comparing the counting value and a comparing threshold to output a level control signal. The signal generating unit is coupled to the comparing unit and configured for generating a pulse width modulation signal according to the level control signal. When the period parameter is odd, the counting value outputted by the counting unit is equal to a middle value in the two continuous clock cycles.
摘要翻译： 提供脉宽调制信号生成电路和脉宽调制信号生成方法。 时钟发生器被配置为产生包括多个脉冲的时钟信号。 计数单元耦合到时钟发生器，并且被配置为存储周期参数，并且通过基于周期参数和双向计数模式对时钟信号的脉冲进行计数来输出计数值。 比较单元耦合到计数单元，并且被配置为比较计数值和比较阈值以输出电平控制信号。 信号产生单元耦合到比较单元，用于根据电平控制信号产生脉宽调制信号。 当周期参数为奇数时，由计数单元输出的计数值等于两个连续时钟周期中的中间值。
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公开(公告)号：US09419625B2
公开(公告)日：2016-08-16
申请号：US14472995
申请日：2014-08-29
CPC分类号： H03K21/023 , H03K21/40
摘要： A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
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公开(公告)号：US09306575B2
公开(公告)日：2016-04-05
申请号：US14625553
申请日：2015-02-18
申请人： Aviacomm Inc.
发明人： Shih Hsiung Mo , Yan Cui , Chung-Hsing Chang
CPC分类号： H03K21/08 , H03B5/02 , H03B19/00 , H03B2200/0048 , H03B2200/0072 , H03K5/00006 , H03K21/023
摘要： One embodiment of the present invention provides a synthesizer. The synthesizer includes one or more tunable oscillators, a frequency-dividing circuit coupled to the tunable oscillators, and a multiplexer coupled to the frequency-dividing circuit. The frequency-dividing circuit includes a number of frequency dividers, and is configured to generate a number of frequency-dividing outputs. At least one frequency-dividing output has a different frequency division factor. The multiplexer is configured to select a frequency-dividing output.
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9.发明申请公开(公告)号：US20160072509A1
公开(公告)日：2016-03-10
申请号：US14805178
申请日：2015-07-21
发明人： Hailong JIA
IPC分类号： H03K21/02
CPC分类号： H03K21/026 , G06F1/08 , H03K21/00 , H03K21/023 , H03K21/38 , H03K23/00 , H03K23/586 , H03L7/193 , H03L7/1974
摘要： A multi-modulus frequency divider includes a frequency division module, a frequency selection module, and a retiming module. The frequency division module is configured to receive an input signal and perform mufti-mode frequency processing on the input signal, so as to generate and output a plurality of divided signals to the frequency selection module. The frequency selection module is configured to receive the plurality of divided signals from the frequency division module, select a divided signal having a desired frequency from among the plurality of divided signals, and output the selected divided signal to the retiming module. The retiming module is configured to receive the selected divided signal from the frequency selection module, perform a retiming operation on the selected divided signal, and output a retimed selected divided signal.
摘要翻译： 多模式分频器包括分频模块，频率选择模块和重定时模块。 分频模块被配置为接收输入信号并对输入信号执行多模式频率处理，以便产生并输出多个分频信号给频率选择模块。 频率选择模块被配置为从分频模块接收多个分频信号，从多个分频信号中选择具有期望频率的分频信号，并将选择的分频信号输出到重定时模块。 重定时模块被配置为从频率选择模块接收所选择的分频信号，对选择的分频信号执行重新定时操作，并输出重新定时的选择的分频信号。
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公开(公告)号：US09184752B2
公开(公告)日：2015-11-10
申请号：US14020239
申请日：2013-09-06
申请人： Synopsys, Inc.
CPC分类号： H03K21/023 , H03K23/662 , H03K23/68
摘要： A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift.
摘要翻译： 描述了将高速数字时钟除以分数值的数字电路。 该电路使用分频器电路，并将分频器时钟相移一小段相位，以实现所需的分数除法。 使用时钟多路复用器来执行时钟偏移，并且使用屏蔽多路复用器来消除时钟偏移期间的毛刺。
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