公开(公告)号：US20200014950A1

公开(公告)日：2020-01-09

申请号：US16572323

申请日：2019-09-16

申请人： Panasonic Intellectual Property Corporation of America

发明人： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC分类号： H04N19/51 ,  H04N19/182 ,  H04N19/176

摘要： An image decoder includes circuitry and a memory, wherein the circuitry, in operation, performs a boundary smoothing operation along a boundary between a first partition having a triangular shape and a second partition having a triangular shape that are split from an image block. The boundary smoothing operation includes: first-deriving a first motion vector for the first partition from a first set of motion vector candidates; second-deriving a second motion vector for the second partition from a second set of motion vector candidates; first-predicting first values of a set of pixels of the first partition along the boundary, using the first motion vector; second-predicting second values of the set of pixels of the first partition along the boundary, using the second motion vector; weighting the first values and the second values; and decoding the first partition using the weighted first values and the weighted second values.

公开(公告)号：US20200014947A1

公开(公告)日：2020-01-09

申请号：US16573517

申请日：2019-09-17

申请人： Panasonic Intellectual Property Corporation of America

发明人： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC分类号： H04N19/44 ,  H04N19/513 ,  H04N19/139 ,  H04N19/105 ,  H04N19/176

摘要： An image decoder includes circuitry and a memory, wherein the circuitry, in operation, performs a boundary smoothing operation along a boundary between a first partition having a triangular shape and a second partition having a triangular shape that are split from an image block. The boundary smoothing operation includes: in response to determining to perform the boundary smoothing operation; first-predicting first values of a set of pixels of the first partition along the boundary, using a first motion vector for the first partition; second-predicting second values of the set of pixels of the first partition along the boundary, using a second motion vector for the second partition; weighting the first values and the second values; and decoding the first partition using the weighted first values and the weighted second values.

公开(公告)号：US20180316918A1

公开(公告)日：2018-11-01

申请号：US15915588

申请日：2018-03-08

申请人： Panasonic Intellectual Property Corporation of America

发明人： Virginie DRUGEON ,  Takahiro NISHI ,  Ryuichi KANOH ,  Tadamasa TOMA

IPC分类号： H04N19/117 ,  H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/82

摘要： An encoding device which further improves coding technique includes processing circuitry and memory. By using the memory, the processing circuitry: performs filtering on a pixel value of a current reference sample to be processed included in reference samples located on a left of or above a current block to be predicted, using pixel values of the reference samples; generates a prediction image by performing intra prediction using the filtered pixel value of the current reference sample. When performing the filtering, the processing circuitry: determines a weight for each reference sample, based on a distance between the reference sample and the current reference sample and a difference in pixel value between the same; and performs filtering on the pixel value of the current reference sample by weighted addition using each of the pixel values of the reference samples and the weight determined for each reference sample.

公开(公告)号：US20240146925A1

公开(公告)日：2024-05-02

申请号：US18390668

申请日：2023-12-20

申请人： Panasonic Intellectual Property Corporation of America

发明人： Masato OHKAWA ,  Hideo SAITOU ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Ryuichi KANOH

IPC分类号： H04N19/12 ,  H04N19/124 ,  H04N19/18 ,  H04N19/625

CPC分类号： H04N19/12 ,  H04N19/124 ,  H04N19/18 ,  H04N19/625 ,  H04N19/619

摘要： An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: performs a first transform on a residual signal of the current block using a first transform basis to generate first transform coefficients; and performs a second transform on the first transform coefficients using a second transform basis to generate second transform coefficients and quantizes the second transform coefficients, when the first transform basis is the same as a predetermined transform basis; and quantizes the first transform coefficients without performing the second transform, when the first transform basis is different from the predetermined transform basis.

公开(公告)号：US20240129516A1

公开(公告)日：2024-04-18

申请号：US18390148

申请日：2023-12-20

申请人： Panasonic Intellectual Property Corporation of America

发明人： Takashi HASHIMOTO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Ryuichi KANOH

IPC分类号： H04N19/513 ,  H04N19/105 ,  H04N19/176

CPC分类号： H04N19/513 ,  H04N19/105 ,  H04N19/176

摘要： A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.

公开(公告)号：US20240089431A1

公开(公告)日：2024-03-14

申请号：US18516252

申请日：2023-11-21

申请人： Panasonic Intellectual Property Corporation of America

发明人： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC分类号： H04N19/117 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186

CPC分类号： H04N19/117 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186

摘要： An encoder includes processing circuitry and a memory coupled to the processing circuitry. Using the memory, the processing circuitry is configured to: change values of pixels in a first block and a second block to filter a boundary between the first block and the second block. The pixels include type one pixels and type two pixels different from the type one pixels. The first set of filter coefficients applied to the type one pixels in the first block and the second set of filter coefficients applied to the type one pixels in the second block are selected to be asymmetrical with respect to the boundary.

公开(公告)号：US20240056598A1

公开(公告)日：2024-02-15

申请号：US18383205

申请日：2023-10-24

申请人： Panasonic Intellectual Property Corporation of America

发明人： Ryuichi KANOH ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Takahiro NISHI

IPC分类号： H04N19/52 ,  H04N19/176 ,  H04N19/124 ,  H04N19/122 ,  H04N19/44

CPC分类号： H04N19/52 ,  H04N19/176 ,  H04N19/124 ,  H04N19/122 ,  H04N19/44

摘要： An encoder includes circuitry and memory. Using the memory, the circuitry performs a primary transform on a derived prediction error, performs a secondary transform on a result of the primary transform, quantizes a result of the secondary transform, and encodes a result of the quantization as data of an image. When a current block to be processed has a predetermined shape, the encoder performs the secondary transform using, among secondary transform basis candidates that are secondary bases usable in the secondary transform, only a secondary transform basis candidate having a size that is not largest size containable in the current block.

公开(公告)号：US20230421762A1

公开(公告)日：2023-12-28

申请号：US18462232

申请日：2023-09-06

申请人： Panasonic Intellectual Property Corporation of America

发明人： Sughosh Pavan SHASHIDHAR ,  Hai Wei SUN ,  Chong Soon LIM ,  Ru Ling LIAO ,  Han Boon TEO ,  Jing Ya LI ,  Takahiro NISHI ,  Kiyofumi ABE ,  Ryuichi KANOH ,  Tadamasa TOMA

IPC分类号： H04N19/119 ,  H04N19/176 ,  H04N19/423 ,  H04N19/63

CPC分类号： H04N19/119 ,  H04N19/176 ,  H04N19/423 ,  H04N19/63

摘要： An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: splits the current block into a first sub block, a second sub block, and a third sub block in a first direction, the second sub block being located between the first sub block and the third sub block; prohibits splitting the second sub block into two partitions in the first direction; and encodes the first sub block, the second sub block, and the third sub block.

公开(公告)号：US20230412795A1

公开(公告)日：2023-12-21

申请号：US18242133

申请日：2023-09-05

申请人： Panasonic Intellectual Property Corporation of America

发明人： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH

IPC分类号： H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186

CPC分类号： H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186

摘要： An encoder includes memory and circuitry. The circuitry, using the memory, (i) selects a mode from among a plurality of modes each for deriving a motion vector, and derives a motion vector for a current block via the selected mode, and (ii) performs inter prediction encoding on the current block, using the derived motion vector, via one of a skip mode and a non-skip mode different from the skip mode. The plurality of modes include a plurality of first modes each for predicting the motion vector for the current block based on an encoded block neighboring the current block without encoding information indicating a motion vector into a stream. When a second mode included in the plurality of first modes is selected, the current block is encoded via the non-skip mode regardless of presence or absence of a residual coefficient.

公开(公告)号：US20230396761A1

公开(公告)日：2023-12-07

申请号：US18451690

申请日：2023-08-17

申请人： Panasonic Intellectual Property Corporation of America

发明人： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC分类号： H04N19/117 ,  H04N19/103 ,  H04N19/176 ,  H04N19/182

CPC分类号： H04N19/117 ,  H04N19/103 ,  H04N19/176 ,  H04N19/182

摘要： Various embodiments provide a decoder configured to select a filter based on a block size of a first block and a block size of a second block in an image, and change values of pixels in the first block and the second block. The filter includes a first set of multipliers and a first set of offsets for the first block, and a second set of multipliers and a second set of offsets for the second block. The values of the pixels in the first block and the second block are changed by performing multiplication with each multiplier in the first set of multipliers, by performing multiplication with each multiplier in the second set of multipliers, and by using the first set of offsets and the second set of offsets.