公开(公告)号：US20210027701A1

公开(公告)日：2021-01-28

申请号：US16852630

申请日：2020-04-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Hyun PARK ,  Bon Yong KOO ,  Yu Jin LEE ,  Kyung Hoon CHUNG ,  Chong Chul CHAI

IPC: G09G3/325 ,  G09G3/3291 ,  G09G3/36

Abstract: A pixel including: a light-emitting element; a first transistor including a first electrode coupled to a power source and a second electrode coupled to the light-emitting element; a first capacitor between a second and a third node; a second transistor between the third node and a data line and turned on by a scan signal; a third transistor between a first node and the second node and turned on by a first control signal; a fourth transistor between the power source and the third node and turned on by a second control signal; a fifth transistor between the power source and the first electrode of the first transistor and turned on by an emission control signal; a sixth transistor between the second node and the light-emitting element and turned on by a previous emission control signal; and a second capacitor between the power source and the first node.

公开(公告)号：US20200381507A1

公开(公告)日：2020-12-03

申请号：US16869673

申请日：2020-05-08

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyun PARK ,  Dong Woo KIM ,  Sung Jae MOON ,  Kang Moon JO

IPC: H01L27/32 ,  H01L49/02

Abstract: The present disclosure relates to a display device, and the display device according to an exemplary embodiment of the present inventive concept includes: a first pixel circuit portion including at least one transistor; a second pixel circuit portion including at least one transistor; a first pixel electrode electrically connected to the first pixel circuit portion; a second pixel electrode electrically connected to the second pixel circuit portion; a first data line electrically connected to the first pixel circuit portion; and a second data line electrically connected to the second pixel circuit portion, wherein the first data line and the second data line are arranged adjacent to each other along a first direction, and the second pixel electrode overlaps the first data line and the second data line in a plan view.

公开(公告)号：US20200266260A1

公开(公告)日：2020-08-20

申请号：US16782899

申请日：2020-02-05

Applicant: Samsung Display Co., LTD.

Inventor： Jun Hyun PARK ,  Kang Moon JO ,  Dong Woo KIM

IPC: H01L27/32 ,  H01L27/12

Abstract: A display device includes: a substrate; a first conductive layer including a lower pattern disposed on the substrate; an active layer including a first active pattern disposed on the first conductive layer; and a second conductive layer including a first gate electrode disposed on the active layer, wherein the first gate electrode overlaps a first channel region included in the first active pattern, the lower pattern overlaps the first active pattern, and the first active pattern does not cross an edge of the lower pattern.

公开(公告)号：US20200219962A1

公开(公告)日：2020-07-09

申请号：US16735990

申请日：2020-01-07

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Hyun PARK ,  Dong Woo KIM ,  Sung Jae MOON ,  Kang Moon JO

IPC: H01L27/32 ,  G09G3/3291 ,  G09G3/3258

Abstract: An organic light emitting diode display according to exemplary embodiments includes: a data wire including a data line disposed in a display area and a first data line disposed in a peripheral area; a driving voltage wire including a driving voltage line disposed in the display area and a first driving voltage line disposed in the peripheral area and extending in a first direction; and a driving low voltage wire including a cathode covering the display area and formed to the peripheral area and a first driving low voltage connection portion connected to the cathode and disposed in the peripheral area, wherein the first driving low voltage connection portion includes a first portion and a second portion having a different width than the first portion.

公开(公告)号：US20200184898A1

公开(公告)日：2020-06-11

申请号：US16707994

申请日：2019-12-09

Applicant: Samsung Display Co., Ltd.

Inventor： Yang Hwa CHOI ,  Jun Hyun PARK ,  Dong Woo KIM ,  Kang Moon JO ,  Sung Jae MOON ,  An Su LEE ,  Woong Sik CHOI

IPC: G09G3/3266 ,  G09G3/3258 ,  G09G3/3275

Abstract: A stage of a scan driver includes: a first driving controller for controlling a voltage of a first node and a voltage of a second node; a second driving controller for controlling a voltage of a first driving node, based on a sensing-on signal, a next carry signal, a first control clock signal, a second control clock signal, the voltage of the first node, and a voltage of a sampling node, and controlling a voltage of a second driving node, based on the voltage of the sampling node and the voltage of the first driving node; an output buffer for outputting a carry signal, the first scan signal, and the second scan signal; and a coupling controller. The second driving controller maintains the voltage of the first driving node as a gate-off voltage in response to the voltage of the second driving node and a third control clock signal.

公开(公告)号：US20190237020A1

公开(公告)日：2019-08-01

申请号：US16264199

申请日：2019-01-31

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyun PARK ,  Cheol Gon LEE ,  Yang Hwa CHOI

IPC: G09G3/3258 ,  G09G3/3266

CPC classification number: G09G3/3258 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2330/021

Abstract: An organic light emitting (OLE) display device includes pixels connected to scan lines (SLs), data lines (DLs), and a first control line (FCL) commonly connected to the pixels. Each pixel includes: an OLE diode connected between a first power source (PS) and a second PS; a first transistor (TFT1) connected between the first PS and the OLE diode, a gate electrode (GE) of the TFT1 being connected to a first node (N1); a second transistor (TFT2) connected between the N1 and a second node (N2), a GE of the TFT2 being connected to a SL; a third transistor (TFT3) connected between the N2 and a third node (N3), the N3 being connected between the TFT1 and the OLED, a GE of the TFT3 being connected to the FCL; a first capacitor connected between the first PS and the N1; and a second capacitor connected between the N2 and a DL.

公开(公告)号：US20190035336A1

公开(公告)日：2019-01-31

申请号：US15989673

申请日：2018-05-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Hyun PARK ,  Young Wan SEO ,  An Su LEE ,  Kang Moon JO ,  Chong Chul CHAI

IPC: G09G3/3266 ,  G09G3/3225

Abstract: An organic light emitting display device includes a plurality of pixels. A pixel on an ith horizontal line includes a first transistor coupled between a first power source and a first node and having a gate electrode coupled to a second node. An organic light emitting diode is coupled between the first node and a second power source. A second transistor is coupled between the second and third nodes and is turned on when a first scan signal is supplied to an ith first scan line. A third transistor is coupled between the third and first nodes. A first capacitor is coupled between an ith control line and the second node. A second capacitor is coupled between the third node and a data line. The pixels are simultaneously driven during first, second, and third periods of a frame period and sequentially driven during a fourth period of the frame period.

公开(公告)号：US20180018921A1

公开(公告)日：2018-01-18

申请号：US15647703

申请日：2017-07-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Hyun PARK ,  Sung Hwan KIM ,  Byung Geun JUN

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2310/0221 ,  G09G2310/0286

Abstract: A stage includes an output, first and second controllers, and first and second inputs. The output supplies a scan signal to a first output terminal and a carry signal to a second output terminal based on first and second node voltages and a first clock signal supplied to a first input terminal. The first controller controls a third node voltage based on a voltage of the second output terminal. The second controller controls the second node voltage based on the first clock signal supplied to the first input terminal and the third node voltage. The first input controls the first and third node voltages based on a carry signal of a previous stage supplied to a second input terminal. The second input controls the first and third node voltages based on the second node voltage and a carry signal of a next stage supplied to a third input terminal.

公开(公告)号：US20170025447A1

公开(公告)日：2017-01-26

申请号：US14995675

申请日：2016-01-14

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyun PARK ,  Sung Hwan KIM ,  Se Young SONG ,  Kyoung Ju SHIN

IPC: H01L27/12 ,  H01L49/02

CPC classification number: H01L27/1255 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L28/60

Abstract: A display device includes a substrate, a thin film transistor, a storage electrode, a pixel electrode, and a common electrode. The thin film transistor is disposed on the substrate and includes a drain electrode and a semiconductor layer. The storage electrode is disposed at a same layer as the semiconductor layer. The pixel electrode is disposed on the substrate and is electrically connected to the drain electrode. The common electrode is disposed on the substrate.

Abstract translation: 显示装置包括基板，薄膜晶体管，存储电极，像素电极和公共电极。 薄膜晶体管设置在基板上，并且包括漏电极和半导体层。 存储电极设置在与半导体层相同的层。 像素电极设置在基板上并与漏电极电连接。 公共电极设置在基板上。

公开(公告)号：US20160240129A1

公开(公告)日：2016-08-18

申请号：US14920596

申请日：2015-10-22

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee KIM ,  Ji-Sun KIM ,  Jun Hyun PARK ,  Young Wan SEO ,  Jae Keun LIM ,  Chong Chul CHAI

IPC: G09G3/20 ,  H03K19/0175

CPC classification number: G09G3/2092 ,  G09G2310/0286 ,  H03K19/017509

Abstract: A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node.

Abstract translation: 根据本发明构思的示例性实施例的门电路包括多个级，每个级接收时钟信号并输出​​门信号和进位信号。 多个级中的一个包括第一晶体管和第一晶体管，第一晶体管的第一端子和控制端子彼此连接，并且前一级之前的级的进位信号被输入到第一端子和控制端子，第二晶体管的第二晶体管 前级的门信号被输入到第一端子，控制端子与第一晶体管的第二端子连接，输出端子连接到第一节点。