公开(公告)号：US06636438B2

公开(公告)日：2003-10-21

申请号：US10190635

申请日：2002-07-08

申请人： Tomoko Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/08

摘要： The present invention is a decoder for control gate lines of a twin MONOS flash memory array. Decoder units connected to each control gate line of the memory are controlled to provide select, override and unselect voltages to perform read, program and erase operations. The decoder units are divided into odd and even addressing where separate voltages can be applied control gates of to adjacent memory cells. Override voltages, which prevent operations of a selected cell from affecting adjacent memory cell storage sites, can be applied to the control gates of immediate neighboring cells of the selected sell. Unselected voltages can be applied to beyond the immediate neighboring cells to further prevent disturb conditions in remote cells.

摘要翻译： 本发明是用于双MONOS闪存阵列的控制栅极线的解码器。 连接到存储器的每个控制栅极线的解码器单元被控制以提供选择，覆盖和取消选择电压以执行读取，编程和擦除操作。 解码器单元被划分为奇数寻址和偶数寻址，其中单独的电压可以被施加到相邻存储器单元的控制门。 可以将防止所选择的单元的操作影响相邻的存储单元存储位置的覆盖电压施加到所选择的销售的直接相邻单元的控制门。 未选择的电压可以施加到紧邻的相邻电池之外，以进一步防止远程电池中的干扰状况。

公开(公告)号：US6069824A

公开(公告)日：2000-05-30

申请号：US261138

申请日：1999-03-03

申请人： Makoto Kojima ,  Tomoko Ogura

发明人： Makoto Kojima ,  Tomoko Ogura

IPC分类号： G11C16/06 ,  G11C16/02 ,  G11C16/04 ,  G11C16/30

CPC分类号： G11C16/0416 ,  G11C16/30

摘要： A plurality of pull-down transistors, each grounding a source line at discrete positions, are provided in order that current, flowing from bit lines through some of nonvolatile memory cells having lower threshold voltages into the source line, is not concentrated at a single pull-down transistor in a source line driver during a read cycle.

摘要翻译： 提供多个下拉晶体管，每个在离散位置处将源极线接地，以便从位线流过具有较低阈值电压的一些非易失性存储单元流入源极线的电流不集中在单个拉 在读取周期期间在源极线驱动器中的下降晶体管。