公开(公告)号：US07443196B2

公开(公告)日：2008-10-28

申请号：US11375363

申请日：2006-03-13

申请人： Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit

发明人： Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

摘要： Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile.

摘要翻译： 本发明的一些实施例提供了一种可配置的集成电路（IC），其包括分成多个瓦片的多个可配置电路。 可配置IC还包括用于将配置数据加载到IC中的配置网络，其中配置数据用于配置几个可配置电路。 在一些实施例中，配置网络包括在瓦片之间的几个边界处的若干寄存器，其中寄存器允许多个配置数据组同时被路由到多个瓦片。 在一些实施例中，配置网络包括几个瓦片处的几个地址计数器，其中每个地址计数器允许为瓦片加载一个地址，然后基于通过配置网络发送的递增指令来连续递增。 至少由特定瓦片的地址计数器指定的两个不同的地址标识特定瓦片内的两个不同的资源。

公开(公告)号：US20070241772A1

公开(公告)日：2007-10-18

申请号：US11081867

申请日：2005-03-15

申请人： Herman Schmit ,  Jason Redgrave

发明人： Herman Schmit ,  Jason Redgrave

IPC分类号： H03K19/173

CPC分类号： H03K19/17728 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/17736 ,  H03K19/1776 ,  H01L2924/00014

摘要： Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. Each memory tiles includes a set of routing circuits and a memory array for storing data on which the logic circuit perform computation. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

摘要翻译： 本发明的一些实施例提供了一种可配置的IC，其包括若干可配置的计算瓦片和几个存储器瓦片。 每个计算瓦片具有用于可配置地执行多个计算的一组可配置逻辑电路和一组可配置路由电路。 瓦片的路由电路可配置地在可配置逻辑电路之间路由信号。 每个存储器片包括一组路由电路和用于存储逻辑电路执行计算的数据的存储器阵列。 在该IC中，至少第一存储器块具有与至少第二计算块相同的一组可配置路由电路。

公开(公告)号：US20130038347A1

公开(公告)日：2013-02-14

申请号：US13550589

申请日：2012-07-16

申请人： Herman Schmit ,  Jason Redgrave

发明人： Herman Schmit ,  Jason Redgrave

IPC分类号： H03K19/173

CPC分类号： G06F7/506 ,  G06F2207/3868 ,  H03K19/173

摘要： Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

摘要翻译： 一些实施例提供了包括若干可配置逻辑电路的可配置IC，其中逻辑电路包括若干组相关联的可配置逻辑电路。 对于每组几组相关联的可配置逻辑电路，可重新配置的IC还包括一个执行多达N个进位操作的进位电路，其中N大于2。

公开(公告)号：US07765249B1

公开(公告)日：2010-07-27

申请号：US11269518

申请日：2005-11-07

申请人： Daniel J. Pugh ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

发明人： Daniel J. Pugh ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC分类号： G06F7/38 ,  G06F7/52

CPC分类号： G06F7/5324 ,  H03K19/17728 ,  H03K19/17736

摘要： Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions on a set of inputs. The IC also includes several input select interconnect circuits for selecting the input set supplied to each configurable logic circuit. Each input select interconnect circuit is associated with a particular configurable logic circuit. When a configurable logic circuit is used to perform a multiplication operation, at least one of its associated input select interconnect circuits performs a logic operation that implements part of the multiplication operation.

摘要翻译： 本发明的一些实施例提供了可配置的集成电路（“IC”）。 可配置IC包括一组可配置逻辑电路，用于在一组输入上可配置地执行一组功能。 IC还包括用于选择提供给每个可配置逻辑电路的输入组的多个输入选择互连电路。 每个输入选择互连电路与特定的可配置逻辑电路相关联。 当可配置逻辑电路用于执行乘法运算时，其相关联的输入选择互连电路中的至少一个执行实现乘法运算的一部分的逻辑运算。

公开(公告)号：US07489162B1

公开(公告)日：2009-02-10

申请号：US11293856

申请日：2005-12-01

申请人： Herman Schmit ,  Jason Redgrave

发明人： Herman Schmit ,  Jason Redgrave

IPC分类号： H03K19/173

CPC分类号： H03K19/17756 ,  H03K19/1776 ,  H03K19/17776

摘要： Some embodiments provide a reconfigurable IC. This reconfigurable IC includes a set of reconfigurable circuits for reconfigurably performing a set of operations in more than one reconfiguration cycle. The reconfigurable IC also includes a set of reconfigurable circuits that perform a storage operation during one reconfiguration cycle and perform a non-storage operation during a second reconfiguration cycle. At least two of these reconfigurable circuits are communicatively coupled to operate as a data register during at least two reconfiguration cycles.

摘要翻译： 一些实施例提供可重新配置的IC。 该可重新配置的IC包括一组可重配置电路，用于在多于一个的重新配置周期中可重配置地执行一组操作。 可重配置IC还包括一组可重构电路，其在一个重新配置周期期间执行存储操作并且在第二重新配置周期期间执行非存储操作。 这些可重构电路中的至少两个通信地耦合以在至少两个重新配置周期期间作为数据寄存器操作。

公开(公告)号：US20080224730A1

公开(公告)日：2008-09-18

申请号：US11375363

申请日：2006-03-13

申请人： Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit

发明人： Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

摘要： Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile.

摘要翻译： 本发明的一些实施例提供了一种可配置的集成电路（IC），其包括分成多个瓦片的多个可配置电路。 可配置IC还包括用于将配置数据加载到IC中的配置网络，其中配置数据用于配置几个可配置电路。 在一些实施例中，配置网络包括在瓦片之间的几个边界处的若干寄存器，其中寄存器允许多个配置数据组同时被路由到多个瓦片。 在一些实施例中，配置网络包括几个瓦片处的几个地址计数器，其中每个地址计数器允许为瓦片加载一个地址，然后基于通过配置网络发送的递增指令来连续递增。 至少由特定瓦片的地址计数器指定的两个不同的地址标识特定瓦片内的两个不同的资源。

公开(公告)号：US20070242529A1

公开(公告)日：2007-10-18

申请号：US11745442

申请日：2007-05-07

申请人： Jason Redgrave ,  Herman Schmit

发明人： Jason Redgrave ,  Herman Schmit

IPC分类号： G11C7/00

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： The invention relates to accessing contents of memory cells. Some embodiments include a memory structure that has a first cell, a second cell, and a sense amplifier. The first cell stores a first value. The first and second cells are connected to the sense amplifier by one or more bit lines. The sense amplifier receives the first value stored by the first cell by using the one or more bit lines and drives the received first value to the second cell through the one or more bit lines. The receiving and driving occur in a single clock cycle. In some embodiments, the second cell outputs the first value. The memory structure of some embodiments also includes a third cell connected to the sense amplifier by the one or more bit lines. The sense amplifier drives a second value to the third cell while the second cell outputs the first value. Other embodiments include a method for accessing data in a memory structure. The method receives a value stored by a first cell; and drives the received value to a second cell. The receiving and driving occur in a single time period. In some embodiments, the method also includes driving a first value to the second cell in a first time period and driving a second value to a third cell in a second time period. In these embodiments, the second cell outputs the first value during the second time period and the third cell outputs the second value during a third time period.

摘要翻译： 本发明涉及访问存储器单元的内容。 一些实施例包括具有第一单元，第二单元和读出放大器的存储器结构。 第一个单元格存储第一个值。 第一和第二单元通过一个或多个位线连接到读出放大器。 感测放大器通过使用一个或多个位线接收第一单元存储的第一值，并通过一个或多个位线将接收到的第一值驱动到第二单元。 接收和驱动在单个时钟周期内发生。 在一些实施例中，第二单元输出第一值。 一些实施例的存储器结构还包括通过一个或多个位线连接到读出放大器的第三单元。 读出放大器将第二值驱动到第三单元，而第二单元输出第一值。 其他实施例包括用于访问存储器结构中的数据的方法。 该方法接收由第一小区存储的值; 并将接收到的值驱动到第二个单元。 接收和驾驶在单个时间段内发生。 在一些实施例中，该方法还包括在第一时间段内将第一值驱动到第二单元，并且在第二时间段内将第二值驱动到第三单元。 在这些实施例中，第二单元在第二时间段期间输出第一值，而第三单元在第三时间段期间输出第二值。

公开(公告)号：US07242216B1

公开(公告)日：2007-07-10

申请号：US11081809

申请日：2005-03-15

申请人： Herman Schmit ,  Jason Redgrave

发明人： Herman Schmit ,  Jason Redgrave

IPC分类号： H03K19/177

CPC分类号： G11C5/025 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H03K19/17736 ,  H03K19/1776 ,  H01L2924/00014 ,  H01L2924/00

摘要： Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. These tiles are arranged in a particular tile arrangement. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. The configurable IC also has several memory arrays for storing data on which the logic circuit perform computation. The memory arrays are embedded in the tile arrangement between two sets of memory tiles, where each set of memory tiles includes a set of routing circuits. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

摘要翻译： 本发明的一些实施例提供了一种可配置的IC，其包括若干可配置的计算瓦片和几个存储器瓦片。 这些瓦片被布置成特定的瓦片布置。 每个计算瓦片具有用于可配置地执行多个计算的一组可配置逻辑电路和一组可配置路由电路。 瓦片的路由电路可配置地在可配置逻辑电路之间路由信号。 可配置IC还具有多个用于存储逻辑电路执行计算的数据的存储器阵列。 存储器阵列嵌入在两组存储器片之间的瓦片布置中，其中每组存储器瓦片包括一组路由电路。 在该IC中，至少第一存储器块具有与至少第二计算块相同的一组可配置路由电路。

公开(公告)号：US08797062B2

公开(公告)日：2014-08-05

申请号：US13550589

申请日：2012-07-16

申请人： Herman Schmit ,  Jason Redgrave

发明人： Herman Schmit ,  Jason Redgrave

IPC分类号： H03K19/173

CPC分类号： G06F7/506 ,  G06F2207/3868 ,  H03K19/173

摘要： Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

摘要翻译： 一些实施例提供了包括若干可配置逻辑电路的可配置IC，其中逻辑电路包括若干组相关联的可配置逻辑电路。 对于每组几组相关联的可配置逻辑电路，可重新配置的IC还包括一个执行多达N个进位操作的进位电路，其中N大于2。

公开(公告)号：US08115510B2

公开(公告)日：2012-02-14

申请号：US12754603

申请日：2010-04-05

申请人： Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit

发明人： Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

摘要： Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile.

摘要翻译： 本发明的一些实施例提供了一种可配置的集成电路（IC），其包括分成多个瓦片的多个可配置电路。 可配置IC还包括用于将配置数据加载到IC中的配置网络，其中配置数据用于配置几个可配置电路。 在一些实施例中，配置网络包括在瓦片之间的几个边界处的若干寄存器，其中寄存器允许多个配置数据组同时被路由到多个瓦片。 在一些实施例中，配置网络包括几个瓦片处的几个地址计数器，其中每个地址计数器允许为瓦片加载一个地址，然后基于通过配置网络发送的递增指令来连续递增。 至少由特定瓦片的地址计数器指定的两个不同的地址标识特定瓦片内的两个不同的资源。