摘要:
Exemplary embodiments provide for methods and systems that enable frame generation by fields taken from various queues. Protocol control can also or alternatively be distributed so that one or more header fields can be generated separately from other portions of a frame, e.g., the payload. The one or more header fields can be entered into queues from which they are taken to generate frames.
摘要:
Devices, systems and methods for run-time reassignment of the interconnection between devices pertaining to a Physical (PHY) layer and devices pertaining to a Media Access Control (MAC) layer, with no packet loss or with at most one packet lost are provided. The strategies employed by these devices, systems and methods used REMOTE FAULT, PAUSE and IDLE PATTERN messages. The devices may be interconnected via a reconfigurable optical crossbar.
摘要:
Presented is a system and method for distributing a network application across a plurality of geographically dispersed network sites. The system comprises a plurality of network sites connected by a shared network and interconnected by a dedicated non-blocking communication network. The system can use different interconnecting network topologies based on the number of sites to be interconnected. The method balances the network application load and resources across the interconnected network sites based on a distribution policy implemented without burdening the shared network. The method provides redundancy capabilities by detecting the loss of a network site and redistributing the network application load to the remaining network sites.
摘要:
One aspect of the invention is directed to a network element (e.g., node/router/switch, etc) which performs internal packet header compression. In particular, an aspect provides a network element comprising a plurality of ingress elements (e.g. line cards), a plurality of egress elements, and system internal network (e.g. a backplane) for switching between the correct Ingress element and egress element, and applying header compression for the purpose of reducing the bandwidth required between the elements. As such internal “metadata” can be added to the compressed header without increasing, and preferably in some embodiments, actually decreasing, the size of the packets. Typically the headers are uncompressed before exiting the egress element.
摘要:
Systems and methods according to these exemplary embodiments provide for dynamically scalable switching fabrics. A dynamically scalable switching fabric can include a first set of fabric element (FE) interfaces and a second set of FE interfaces, interconnectable by a reconfigurable crossbar. By selectively populating the FE interfaces, different switching capabilities, e.g., bandwidth per processor blade and/or number of processor blades supported, can be achieved. When the population of the FE interfaces is modified, the reconfigurable crossbar can reconfigure the links between FEs. According to one embodiment, a three-stage CLOS architecture can be implemented. According to another embodiment, a multi-plane architecture can be implemented.
摘要:
Systems and methods according to these exemplary embodiments provide for optical interconnection using a combination of an arrayed waveguide grating router (AWGr) and optical crossbar. Optical wavelengths can be flexibly routed from an input port to one or more output ports. Scaling of the system is easily accommodated.
摘要:
The invention relates to an optical backplane, comprising a plurality of component connectors and at least two interconnections configurations interconnecting the component connectors. The at least two interconnections configurations allow a dynamical selection of an interconnections configuration interconnecting the component connectors.
摘要:
The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.