公开(公告)号：US09208114B2

公开(公告)日：2015-12-08

申请号：US13615836

申请日：2012-09-14

申请人： Munenori Maeda ,  Jun Kato ,  Tatsuo Kumano ,  Masahisa Tamura ,  Ken Ilzawa ,  Yasuo Noguchi ,  Toshihiro Ozawa

发明人： Munenori Maeda ,  Jun Kato ,  Tatsuo Kumano ,  Masahisa Tamura ,  Ken Ilzawa ,  Yasuo Noguchi ,  Toshihiro Ozawa

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A storage device being one of a plurality of storage devices storing data includes a memory and a processor coupled to the memory. The processor executes determining, when having received a new request and a new priority information during a preparation for an execution of another update processing, whether a new priority indicated by the new priority information is higher than a priority of the update processing in the preparation. The process including canceling the update processing in the preparation when having determines at the determining that the new priority is higher than the priority of the update processing in the preparation. The process includes forwarding the new request and the new priority information to another storage device when having determined at the determining that the new priority is higher than the priority of the update processing in the preparation.

摘要翻译： 作为存储数据的多个存储装置之一的存储装置包括存储器和耦合到存储器的处理器。 处理器执行在准备执行另一更新处理期间已经接收到新请求和新的优先级信息时确定新的优先级信息指示的新的优先级是否高于准备中的更新处理的优先级。 所述处理包括在确定新的优先级高于准备中的更新处理的优先级时确定准备中的更新处理。 当确定新的优先级高于准备中的更新处理的优先级时，该过程包括将新请求和新的优先级信息转发到另一存储设备。

公开(公告)号：US20130138999A1

公开(公告)日：2013-05-30

申请号：US13604682

申请日：2012-09-06

申请人： Masahisa TAMURA ,  Yasuo Noguchi ,  Toshihiro Ozawa ,  Munenori Maeda ,  Tatsuo Kumano ,  Ken Iizawa ,  Jun Kato

发明人： Masahisa TAMURA ,  Yasuo Noguchi ,  Toshihiro Ozawa ,  Munenori Maeda ,  Tatsuo Kumano ,  Ken Iizawa ,  Jun Kato

IPC分类号： G06F11/16

CPC分类号： G06F11/2071 ,  G06F11/2058 ,  G06F11/2082

摘要： An internode put requesting unit detects a time-out with respect to a put request issued to the next node in the order of a multiplexing chain and notifies a put/get executing unit of the time-out. The put/get executing unit sends an error to the previous node in the order of the multiplexing chain or a client and instructs a put-failed-data synchronizing unit to synchronize data failed to be put, and the put-failed-data synchronizing unit performs a synchronization process. A primary makes other put requests wait until completion of the synchronization process. Furthermore, when having received the error, the client issues a get request to the tail end of the multiplexing chain.

摘要翻译： 节点放置请求单元按照多路复用链的顺序检测对发出给下一个节点的放置请求的超时，并将放弃/获取执行单元通知超时。 投放/获取执行单元按照多路复用链或客户端的顺序向前一个节点发送错误，并且指示放置失败数据同步单元将未被置位的数据和丢失失败的数据同步单元 执行同步过程。 主要让其他放置请求等待，直到完成同步过程。 此外，当接收到错误时，客户机向多路复用链的尾端发出获取请求。

公开(公告)号：US20130138893A1

公开(公告)日：2013-05-30

申请号：US13615836

申请日：2012-09-14

申请人： Munenori MAEDA ,  Jun Kato ,  Tatsuo Kumano ,  Masahisa Tamura ,  Ken Ilzawa ,  Yasuo Noguchi ,  Toshihiro Ozawa

发明人： Munenori MAEDA ,  Jun Kato ,  Tatsuo Kumano ,  Masahisa Tamura ,  Ken Ilzawa ,  Yasuo Noguchi ,  Toshihiro Ozawa

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A storage device being one of a plurality of storage devices storing data includes a memory and a processor coupled to the memory. The processor executes determining, when having received a new request and a new priority information during a preparation for an execution of another update processing, whether a new priority indicated by the new priority information is higher than a priority of the update processing in the preparation. The process including canceling the update processing in the preparation when having determines at the determining that the new priority is higher than the priority of the update processing in the preparation. The process includes forwarding the new request and the new priority information to another storage device when having determined at the determining that the new priority is higher than the priority of the update processing in the preparation.

摘要翻译： 作为存储数据的多个存储装置之一的存储装置包括存储器和耦合到存储器的处理器。 处理器执行在准备执行另一更新处理期间已经接收到新请求和新的优先级信息时确定新的优先级信息指示的新的优先级是否高于准备中的更新处理的优先级。 所述处理包括在确定新的优先级高于准备中的更新处理的优先级时确定准备中的更新处理。 当确定新的优先级高于准备中的更新处理的优先级时，该过程包括将新请求和新的优先级信息转发到另一存储设备。

公开(公告)号：US20090049240A1

公开(公告)日：2009-02-19

申请号：US12190898

申请日：2008-08-13

申请人： Kazuichi Oe ,  Tatsuo Kumano ,  Yasuo Noguchi

发明人： Kazuichi Oe ,  Tatsuo Kumano ,  Yasuo Noguchi

IPC分类号： G06F12/16 ,  G06F12/02

CPC分类号： G06F11/2061 ,  G06F11/2074

摘要： A storage apparatus, method and program are provided. The apparatus includes a management information storing unit that stores management information which defines storage nodes to allocate primary data used as a destination of access and secondary data used as a backup. The apparatus also includes data allocation unit that divides storage nodes 5 into groups, and assigns data allocation destination so that the data allocation destination of the primary data and the data allocation destination of the secondary data with the same content as the primary data are not in the same group. The apparatus also includes an operation mode switching unit that replaces the role of primary data assigned to the storage node which belongs to the group subject to suspension with that of the secondary data that corresponds to the primary data.

摘要翻译： 提供了存储装置，方法和程序。 该装置包括管理信息存储单元，其存储定义存储节点以分配用作访问目的地的主数据的管理信息和用作备份的次要数据。 该设备还包括将存储节点5分成组的数据分配单元，并且分配数据分配目的地，使得具有与主数据相同内容的辅数据的主数据和数据分配目的地的数据分配目的地不在 同一组。 该装置还包括操作模式切换单元，其替换分配给属于与暂停的组的存储节点相对应的主数据的主数据的作用。

公开(公告)号：US5663673A

公开(公告)日：1997-09-02

申请号：US413947

申请日：1995-03-30

申请人： Hirokazu Tanaka ,  Tatsuo Kumano ,  Tetsuji Funaki ,  Takahiro Watai

发明人： Hirokazu Tanaka ,  Tatsuo Kumano ,  Tetsuji Funaki ,  Takahiro Watai

IPC分类号： H03G5/16 ,  H03F1/30 ,  H03F3/30 ,  H03F3/45 ,  H04M19/00 ,  H03F3/26 ,  H03K17/16

CPC分类号： H03F3/3071 ,  H03F1/307

摘要： An output circuit, for minimizing output idle current fluctuations and improve the output voltage range, has first and second transistors connected to first and second power sources, with a plurality of diodes connected to control terminals of the first and second transistors. The output circuit further includes a third transistor having a first terminal connected to the second power source and a second terminal connected to a predetermined position among the plurality of diodes. A predetermined voltage is applied from the diodes to the control terminal of the first transistor when the third transistor is saturated, to bring a level of an output of said output circuit close to a level of the second power source. A fourth transistor, a fifth transistor, a first resistor, and a capacitor are also provided. The forth transistor has a control terminal connected to an output of a differential circuit, and a first terminal connected to the second power source through the first resistor as well as to the control terminals of the third and fifth transistors. A second terminal is connected to the first power source, with the fifth transistor having a first terminal connected to the second power source and a second terminal connected to the control terminal of the second transistor. The capacitor is connected between the control terminal of the fourth transistor and the second terminal of the fifth transistor. This output circuit also limits the output voltage without changing the impedance of the high-impedance input.

摘要翻译： 用于最小化输出空闲电流波动并改善输出电压范围的输出电路具有连接到第一和第二电源的第一和第二晶体管，多个二极管连接到第一和第二晶体管的控制端子。 输出电路还包括具有连接到第二电源的第一端子和连接到多个二极管中的预定位置的第二端子的第三晶体管。 当第三晶体管饱和时，从二极管向第一晶体管的控制端施加预定电压，以使所述输出电路的输出电平接近第二电源的电平。 还提供第四晶体管，第五晶体管，第一电阻器和电容器。 第四晶体管具有连接到差分电路的输出的控制端子，以及通过第一电阻器连接到第二电源的第一端子以及第三和第五晶体管的控制端子。 第二端子连接到第一电源，第五晶体管具有连接到第二电源的第一端子和连接到第二晶体管的控制端子的第二端子。 电容器连接在第四晶体管的控制端和第五晶体管的第二端之间。 该输出电路还限制输出电压，而不改变高阻抗输入的阻抗。

公开(公告)号：US06456141B1

公开(公告)日：2002-09-24

申请号：US09922764

申请日：2001-08-07

申请人： Kazunori Nishizono ,  Tatsuo Kumano

发明人： Kazunori Nishizono ,  Tatsuo Kumano

IPC分类号： G06G719

CPC分类号： H04B10/6933 ,  H03F3/087 ,  H03F3/45973 ,  H03K3/02337 ,  H03K5/007 ,  H03K5/086 ,  H04B10/6911 ,  H04B10/6931

摘要： A current pulse receiving circuit suitable for converting a current pulse converted by a photodetector from a light pulse received in optical communications and outputting a logic level voltage pulse with an accurate pulse width is disclosed. When an output signal from a current-to-voltage converter circuit is detected to have a large amplitude by a large signal detection circuit, an amount of offset cancellation of a DC cancellation circuit is decreased to limit the amplitude of the output signal from the current-to-voltage converter circuit. Since the amplitude of an input signal of an amplifier circuit is limited, tail characteristics at a trailing edge of a pulse are small and an output is provided at an output terminal with an accurate pulse width.