公开(公告)号：US06351016B1

公开(公告)日：2002-02-26

申请号：US09389630

申请日：1999-09-03

申请人： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

发明人： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

摘要： A buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

摘要翻译： 描述了埋地接触点。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US6136633A

公开(公告)日：2000-10-24

申请号：US222272

申请日：1998-12-28

申请人： Dun-Nian Yaung ,  Jin-Yuan Lee ,  Shou-Gwo Wuu

发明人： Dun-Nian Yaung ,  Jin-Yuan Lee ,  Shou-Gwo Wuu

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8244 ,  H01L23/535 ,  H01L27/11 ,  H01L29/78 ,  H01L21/44 ,  H01L21/76 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/743 ,  H01L21/76202 ,  H01L23/535 ,  H01L27/11 ,  H01L29/7833 ,  H01L2924/0002

摘要： A new method of forming an improved buried contact junction is described. A gate oxide layer is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited over the gate oxide layer. A photoresist mask is formed over the first polysilicon layer having an opening over the planned buried contact. The first polysilicon layer not covered by the photoresist mask is etched away. A portion of the photoresist mask at the edges of the opening is cut away to expose a portion of the first polysilicon layer at the edges of the opening. The gate oxide layer not covered by the mask is etched away using a reduced etching selectivity of oxide to silicon so that an upper portion of the first polysilicon layer exposed at the edges of the opening is etched away leaving a thinner first polysilicon layer at the edges of the opening. Ions are implanted through the opening and through the thinner first polysilicon layer into the semiconductor substrate to form the buried contact. The photoresist mask is removed and a second polysilicon layer is deposited overlying the first polysilicon layer and the buried contact to complete formation of the buried contact.

摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅氧化层。 第一多晶硅层沉积在栅极氧化物层上。 在第一多晶硅层上形成光致抗蚀剂掩模，该多晶硅层在预定的埋入触点上具有开口。 未被光致抗蚀剂掩模覆盖的第一多晶硅层被蚀刻掉。 在开口的边缘处的光致抗蚀剂掩模的一部分被切除，以在开口的边缘处露出第一多晶硅层的一部分。 使用氧化物对硅的蚀刻选择性降低，掩模未被掩模覆盖的栅极氧化物层被蚀刻掉，使得在开口边缘暴露的第一多晶硅层的上部被蚀刻掉，在边缘处留下较薄的第一多晶硅层 的开幕。 离子通过开口并通过较薄的第一多晶硅层注入到半导体衬底中以形成埋入触点。 去除光致抗蚀剂掩模，并且沉积覆盖第一多晶硅层和埋入触点的第二多晶硅层以完成掩埋触点的形成。

公开(公告)号：US06040227A

公开(公告)日：2000-03-21

申请号：US86826

申请日：1998-05-29

申请人： Shou-Gwo Wuu ,  Lung Chen ,  Dun-Nian Yaung ,  Yi-Miaw Lin

发明人： Shou-Gwo Wuu ,  Lung Chen ,  Dun-Nian Yaung ,  Yi-Miaw Lin

IPC分类号： H01L21/8244

CPC分类号： B82Y15/00 ,  H01L27/11

摘要： The present invention provides a method of inter-poly oxide (IPO) layer underlying a polysilicon resistor in a memory product. The IPO layer 15 is formed by a modified low pressure SACVD-O.sub.3 -TEOS process that gives the IPO layer a smoother surface and good planarization. This IPO layer gives the overlying polysilicon resistors a more uniform resistance. The method begins by providing a semiconductor structure 10. Next, in an important step, an inter-poly oxide (IPO) layer 11 is formed using low pressure ozone assisted sub-atmospheric chemical vapor deposition (SACVD O.sub.3 -TEOS) process at a pressure between about 20 and 150 torr. A polysilicon resistor 15 is then formed on said inter-poly oxide (IPO) layer. The memory device is completed by forming passivation and conductive layers thereover.

摘要翻译： 本发明提供了存储产品中多晶硅电阻下面的多晶硅氧化物（IPO）层的方法。 IPO层15由改进的低压SACVD-O3-TEOS工艺形成，其使IPO层具有更平滑的表面和良好的平坦化。 该IPO层给予覆盖多晶硅电阻更均匀的电阻。 该方法通过提供半导体结构10开始。接下来，在重要步骤中，使用低压臭氧辅助亚大气压化学气相沉积（SACVD O3-TEOS）工艺在压力下形成多晶氧化物（IPO）层11 约20至150托。 然后在所述多晶氧化物（IPO）层上形成多晶硅电阻器15。 通过在其上形成钝化和导电层来完成存储器件。

公开(公告)号：US08389377B2

公开(公告)日：2013-03-05

申请号：US12753440

申请日：2010-04-02

申请人： Ru-Shang Hsiao ,  Kun-Yu Tsai ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Nai-Wen Cheng

发明人： Ru-Shang Hsiao ,  Kun-Yu Tsai ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Nai-Wen Cheng

IPC分类号： H01L21/76

CPC分类号： H01L27/1464 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14689

摘要： The present disclosure provides methods and apparatus for sensor element isolation in a backside illuminated image sensor. In one embodiment, a method of fabricating a semiconductor device includes providing a sensor layer having a frontside surface and a backside surface, forming a plurality of frontside trenches in the frontside surface of the sensor layer, and implanting oxygen into the sensor layer through the plurality of frontside trenches. The method further includes annealing the implanted oxygen to form a plurality of first silicon oxide blocks in the sensor layer, wherein each first silicon oxide block is disposed substantially adjacent a respective frontside trench to form an isolation feature. A semiconductor device fabricated by such a method is also disclosed.

摘要翻译： 本公开提供了用于背面照明图像传感器中的传感器元件隔离的方法和装置。 在一个实施例中，制造半导体器件的方法包括提供具有前侧表面和后侧表面的传感器层，在传感器层的前侧表面中形成多个前侧沟槽，并且通过多个将氧气注入到传感器层中 的前方的沟渠。 该方法还包括退火注入的氧以在传感器层中形成多个第一氧化硅块，其中每个第一氧化硅块基本上邻近相应的前侧沟槽设置以形成隔离特征。 还公开了通过这种方法制造的半导体器件。

公开(公告)号：US20110241152A1

公开(公告)日：2011-10-06

申请号：US12753440

申请日：2010-04-02

申请人： Ru-Shang Hsiao ,  Kun-Yu Tsai ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Nai-Wen Cheng

发明人： Ru-Shang Hsiao ,  Kun-Yu Tsai ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Nai-Wen Cheng

IPC分类号： H01L27/146 ,  H01L31/18

CPC分类号： H01L27/1464 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14689

摘要： The present disclosure provides methods and apparatus for sensor element isolation in a backside illuminated image sensor. In one embodiment, a method of fabricating a semiconductor device includes providing a sensor layer having a frontside surface and a backside surface, forming a plurality of frontside trenches in the frontside surface of the sensor layer, and implanting oxygen into the sensor layer through the plurality of frontside trenches. The method further includes annealing the implanted oxygen to form a plurality of first silicon oxide blocks in the sensor layer, wherein each first silicon oxide block is disposed substantially adjacent a respective frontside trench to form an isolation feature. A semiconductor device fabricated by such a method is also disclosed.

摘要翻译： 本公开提供了用于背面照明图像传感器中的传感器元件隔离的方法和装置。 在一个实施例中，制造半导体器件的方法包括提供具有前侧表面和背面的传感器层，在传感器层的前侧表面中形成多个前侧沟槽，并且通过多个将氧气注入到传感器层中 的前方的沟渠。 该方法还包括退火注入的氧以在传感器层中形成多个第一氧化硅块，其中每个第一氧化硅块基本上邻近相应的前侧沟槽设置以形成隔离特征。 还公开了通过这种方法制造的半导体器件。

公开(公告)号：US08216905B2

公开(公告)日：2012-07-10

申请号：US12768063

申请日：2010-04-27

申请人： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

发明人： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC分类号： H01L21/336

CPC分类号： H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

摘要： The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.

摘要翻译： 上述有源像素单元结构和制备这种结构的方法能够减少有源像素单元的暗电流和白细胞计数。 制备有源像素单元结构的过程在衬底上引入应力，这可能导致有源像素单元的暗电流和白细胞计数增加。 通过沉积应力层作为预金属介电层的一部分，其应力引起应力，暗电流和白细胞计数都可以减小。 如果有源像素单元的晶体管是NMOS，则载流子迁移率也可以通过拉伸应力层增加。 拉曼光谱可用于测量在沉积应力层之前施加在基底上的应力。

公开(公告)号：US09257463B2

公开(公告)日：2016-02-09

申请号：US13588879

申请日：2012-08-17

申请人： Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Chia-Chan Chen ,  Kuo-Yu Wu ,  Dao-Hong Yang ,  Ming-Hao Chung

发明人： Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Chia-Chan Chen ,  Kuo-Yu Wu ,  Dao-Hong Yang ,  Ming-Hao Chung

IPC分类号： H01L21/336 ,  H01L27/146

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463

摘要： A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation.

摘要翻译： 一种器件包括半导体衬底，半导体衬底中的阱区和金属氧化物半导体（MOS）器件。 MOS器件包括与阱区重叠的栅极电介质，栅极电介质上的栅电极和阱区中的源极/漏极区。 源/漏区和阱区具有相反的导电类型。 第一源漏区域背离栅电极的边缘与阱区域接触以形成结隔离。

公开(公告)号：US20130320418A1

公开(公告)日：2013-12-05

申请号：US13588879

申请日：2012-08-17

申请人： Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Chia-Chan Chen ,  Kuo-Yu Wu ,  Dao-Hong Yang ,  Ming-Hao Chung

发明人： Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Chia-Chan Chen ,  Kuo-Yu Wu ,  Dao-Hong Yang ,  Ming-Hao Chung

IPC分类号： H01L31/113 ,  H01L21/336

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463

摘要： A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation.

摘要翻译： 一种器件包括半导体衬底，半导体衬底中的阱区和金属氧化物半导体（MOS）器件。 MOS器件包括与阱区重叠的栅极电介质，栅极电介质上的栅电极和阱区中的源极/漏极区。 源/漏区和阱区具有相反的导电类型。 第一源漏区域背离栅电极的边缘与阱区域接触以形成结隔离。

公开(公告)号：US08546860B2

公开(公告)日：2013-10-01

申请号：US13494769

申请日：2012-06-12

申请人： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

发明人： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC分类号： H01L31/113 ,  H01L31/173

CPC分类号： H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

摘要： This disclosure relates to an active pixel cell including a shallow trench isolation (STI) structure. The active pixel cell further includes a photodiode neighboring the STI structure, where a first stress resulted from substrate processing prior to deposition of a pre-metal dielectric layer increases dark current and white cell counts of a photodiode of the active pixel cell. The active pixel cell further includes a transistor, where the transistor controls the operation of the active pixel cell. The active pixel cell further includes a stress layer over the photodiode, the STI structure, and the transistor, and the stress layer has a second stress that counters the first stress exerted on the substrate, and the second stress reduces the dark current and the white cell counts caused by the first stress.

摘要翻译： 本公开涉及包括浅沟槽隔离（STI）结构的有源像素单元。 有源像素单元还包括与STI结构相邻的光电二极管，其中在沉积预金属介电层之前由衬底处理产生的第一应力增加了有源像素单元的光电二极管的暗电流和白细胞计数。 有源像素单元还包括晶体管，其中晶体管控制有源像素单元的操作。 有源像素单元还包括光电二极管上的应力层，STI结构和晶体管，并且应力层具有对施加在衬底上的第一应力进行反映的第二应力，并且第二应力减小暗电流和白色 细胞计数由第一次压力引起。

公开(公告)号：US20080217719A1

公开(公告)日：2008-09-11

申请号：US11682633

申请日：2007-03-06

申请人： J. C. Liu ,  C. H. Cheng ,  Chien-Hsien Tseng ,  Alex Hsu ,  Feng-Jia Shiu ,  Shou-Gwo Wuu

发明人： J. C. Liu ,  C. H. Cheng ,  Chien-Hsien Tseng ,  Alex Hsu ,  Feng-Jia Shiu ,  Shou-Gwo Wuu

IPC分类号： H01L31/00 ,  H01L21/76

CPC分类号： H01L27/1463 ,  H01L27/14689

摘要： The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.

摘要翻译： 本公开提供了一种图像传感器半导体器件。 提供具有第一类电导率的半导体衬底。 在半导体衬底中形成多个传感器元件。 在多个传感器元件之间形成隔离特征。 执行离子注入工艺以使用至少两种不同的注入能量形成具有基本上位于隔离特征下的第一类型导电的掺杂区域。