公开(公告)号：US20210013333A1

公开(公告)日：2021-01-14

申请号：US16527042

申请日：2019-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/762 ,  H01L29/20 ,  H01L29/66

Abstract: A high electron mobility transistor, including an active area, a buffer layer on the active area, a channel layer on the buffer layer, a barrier layer on the channel layer, and gate, source and drain on the barrier layer, and a trench isolation structure adjacent and surrounding the channel layer and the barrier layer to apply stress and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor.

公开(公告)号：US20200227324A1

公开(公告)日：2020-07-16

申请号：US16261494

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device includes a substrate having a top surface, a source region in the substrate, a drain region in the substrate, a recessed trench extending from the top surface into the substrate and between the source region and the drain region, a stress-inducing material layer in the recessed trench, a channel layer on the stress-inducing material layer, and a gate structure on the channel layer. The recessed trench has a hexagonal cross-sectional profile.

公开(公告)号：US20190386150A1

公开(公告)日：2019-12-19

申请号：US16046961

申请日：2018-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

Abstract: A nanowire transistor structure includes a substrate. A first nanowire is suspended on the substrate. A first gate line crosses and surrounds the first nanowire. The first gate line includes a first end and a second end. A second gate line crosses and surrounds the first nanowire. The second gate line includes a third end and a fourth end. An interlayer dielectric encapsulates the first end, the second end, the third end and the fourth end. A first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire.

公开(公告)号：US10276446B1

公开(公告)日：2019-04-30

申请号：US15976848

申请日：2018-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Han-Tsun Wang ,  Chang-Hung Chen ,  Po-Yu Yang ,  Mei-Ying Fan ,  Mu-Kai Tsai ,  Guan-Shyan Lin ,  Tsz-Hui Kuo ,  Cheng-Hsiung Chen

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11

Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. A gate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

公开(公告)号：US12224333B2

公开(公告)日：2025-02-11

申请号：US17842814

申请日：2022-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

Abstract: An HEMT with a stair-like compound layer as a drain includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode, a gate electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed between the source electrode and the drain electrode. A first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer. The first P-type III-V compound layer is stair-like.

公开(公告)号：US20240339495A1

公开(公告)日：2024-10-10

申请号：US18195354

申请日：2023-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor channel layer, a second semiconductor channel layer, and an isolation structure. The first semiconductor channel layer, the second semiconductor channel layer, and the isolation structure are disposed above the semiconductor substrate. The isolation structure includes a vertical portion, a first horizontal portion, and a second horizontal portion. The vertical portion is disposed between the first semiconductor channel layer and the second semiconductor channel layer in a horizontal direction. The first horizontal portion is disposed between the first semiconductor channel layer and the semiconductor substrate in a vertical direction. The second horizontal portion is disposed between the second semiconductor channel layer and the semiconductor substrate in the vertical direction. The first horizontal portion and the second horizontal portion are connected with the vertical portion.

公开(公告)号：US20240332421A1

公开(公告)日：2024-10-03

申请号：US18227979

申请日：2023-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66795

Abstract: A semiconductor device includes a first fin structure, an insulating structure, a first groove and a gate structure. The first fin structure is extended along a first direction on a substrate. The insulating structure surrounds the first fin structure. The first groove is extended along the first direction and disposed between the first fin structure and the insulating structure. The first groove exposes a first portion of the substrate. The gate structure is extended along a second direction on the first fin structure. At least a portion of the gate structure is disposed in the first groove. The gate structure includes a gate dielectric layer disposed on the first fin structure and the first portion of the substrate.

公开(公告)号：US12046669B2

公开(公告)日：2024-07-23

申请号：US18206620

申请日：2023-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778

CPC classification number: H01L29/7786 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7787

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A gate is disposed on the second III-V compound layer. The gate includes a first P-type III-V compound layer, an undoped III-V compound layer and an N-type III-V compound layer are deposited from bottom to top. The first P-type III-V compound layer, the undoped III-V compound layer, the N-type III-V compound layer and the first III-V compound layer are chemical compounds formed by the same group III element and the same group V element. A drain electrode is disposed at one side of the gate. A drain electrode is disposed at another side of the gate. A gate electrode is disposed directly on the gate.

公开(公告)号：US11990539B2

公开(公告)日：2024-05-21

申请号：US17148526

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/66462

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate capping layer, a dielectric layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate capping layer is disposed on the semiconductor barrier layer, and the dielectric layer conformally covers the gate capping layer and surrounds the periphery of the gate capping layer. The gate electrode is disposed on the dielectric layer and covers at least one sidewall of the gate capping layer.

公开(公告)号：US20240145594A1

公开(公告)日：2024-05-02

申请号：US17993983

申请日：2022-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a gate structure on the STI and the substrate, forming a patterned mask on the STI and the gate structure, performing an etching process to remove part of the STI for forming a first trench adjacent to one side of the gate structure and a second trench adjacent to another side of the gate structure, and then forming a contact etch stop layer (CESL) on the gate structure and into the first trench and the second trench.