公开(公告)号：US20240030228A1

公开(公告)日：2024-01-25

申请号：US17600143

申请日：2021-09-13

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Tao MA ,  Zhilin WU ,  Fei AI

IPC: H01L27/12

CPC classification number: H01L27/124

Abstract: An array substrate and a display panel are disclosed. The array substrate includes an underlay, a seed layer disposed on one side of the underlay, and a first metal layer disposed on one side of the seed layer and away from the underlay, wherein the first metal layer directly contacts the seed layer. The present application utilizes the seed layer directly contacting the first metal layer to induce crystallization of the first metal layer, so that the first metal layer is formed with larger grains, fewer grain boundaries and less charge carrier scattering, and a resistivity of the first metal layer is decreased.

公开(公告)号：US20230154949A1

公开(公告)日：2023-05-18

申请号：US17281268

申请日：2021-03-11

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Fuhsiung TANG ,  Fan GONG ,  Fei AI ,  Jiyue SONG

IPC: H01L27/146 ,  G06V40/13

CPC classification number: H01L27/14612 ,  G06V40/1318 ,  H01L27/14678

Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, and a switch component and a light-sensing component adjacent to each other and disposed on the substrate. The switch component includes a first semiconductor disposed on the substrate. The light-sensing component includes a second semiconductor disposed on a same layer as the first semiconductor and a light-sensing electrode disposed on a side of the second semiconductor away from the substrate and connected to the second semiconductor. The light-sensing electrode and the second semiconductor constitute a Schottky knot.

公开(公告)号：US20220190185A1

公开(公告)日：2022-06-16

申请号：US17263943

申请日：2020-06-24

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Jianfeng YUAN ,  Fei AI ,  Jiyue SONG

IPC: H01L31/105 ,  H01L27/144 ,  H01L31/20 ,  H01L31/0336 ,  H01L51/42 ,  H01L27/30

Abstract: A positive-intrinsic-negative (PIN) photosensitive device is provided. A p-type semiconductor layer composed of molybdenum oxide and having valence band energy between valence band energy of an intrinsic semiconductor layer and an upper electrode is used to replace a p-type semiconductor layer used in a conventional PIN photodiode, so that the PIN photodiode may be prepared without using borane gas. More, a difference between valence band energy of the p-type semiconductor layer and the intrinsic semiconductor layer is used to transport holes located in a valence band, so that it is unnecessary to use an active layer of a thin film transistor, so that the PIN photosensitive device may be stacked on the thin film transistor to reduce aperture ratio loss of a display panel.

公开(公告)号：US20210041733A1

公开(公告)日：2021-02-11

申请号：US16613419

申请日：2019-10-18

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Fei AI ,  Dewei Song

IPC: G02F1/1333 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  G06F3/041

Abstract: An array substrate, a method of manufacturing the same and a touch display panel are disclosed. An inorganic insulating layer, a plurality of common electrodes and a passivation layer are sequentially manufactured on a substrate formed with a plurality of thin film transistors and a plurality of touch signal lines. The passivation layer and the inorganic insulating layer are patterned to form a plurality of first via holes exposing drain electrodes of the thin film transistors and the touch signal lines, and to form a plurality of second via holes exposing the common electrodes in such a manner that the touch signal lines and the common electrodes are bridged through the touch electrodes formed on a surface of the passivation layer.

公开(公告)号：US20200279869A1

公开(公告)日：2020-09-03

申请号：US16475684

申请日：2019-04-30

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Fei AI ,  Dewei SONG

IPC: H01L27/12 ,  H01L21/768 ,  H01L29/786 ,  H01L29/66

Abstract: A method of manufacturing an array substrate and an array substrate are provided. The method of manufacturing the array substrate includes forming a first metal layer on a substrate, wherein the first metal layer includes a plurality of first metal lines and a plurality of intermittent second metal lines, forming an interlayer dielectric insulating layer on the substrate and the first metal layer, and forming an intermittent data line on the interlayer dielectric insulating layer and the first metal layer, wherein the intermittent data line contacts the two ends of each of the intermittent second metal lines through the via holes.