公开(公告)号：US07412672B1

公开(公告)日：2008-08-12

申请号：US11104651

申请日：2005-04-13

申请人： Laung-Terng Wang ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Khader S. Abdel-Hafez

发明人： Laung-Terng Wang ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Khader S. Abdel-Hafez

IPC分类号： G06F17/50

CPC分类号： G01R31/3177 ,  G01R31/318533 ,  G01R31/31926

摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor.

公开(公告)号：US20060156122A1

公开(公告)日：2006-07-13

申请号：US11350949

申请日：2006-02-10

申请人： Laung-Terng Wang ,  Xiaoqing Wen ,  Boryau Sheu

发明人： Laung-Terng Wang ,  Xiaoqing Wen ,  Boryau Sheu

IPC分类号： G01R31/28

CPC分类号： G01R31/318547 ,  G01R31/318536

摘要： A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.

摘要翻译： 一种用于选择性地遮蔽第一选定扫描单元220中的未知（'x“）捕获的扫描数据的方法和装置，其传播通过扫描链221，用于测试，调试，诊断和屈服改善基于扫描的集成电路207 选择扫描测试模式232或选择自检模式。 基于扫描的集成电路207包含多个扫描链221，多个图案生成器208，多个图案压缩器213，每个扫描链221包括串联耦合的多个扫描单元220,222。 该方法和装置还包括输入掩模控制器211和嵌入在第二选择的扫描单元222的扫描数据输入路径上的输出屏蔽网络212，或者设置/复位控制器控制第二选择的扫描单元的选定的设置/复位输入 。 还提出了一种用于合成输出掩模控制器211和设置/复位控制器的合成方法。

公开(公告)号：US07058869B2

公开(公告)日：2006-06-06

申请号：US10762571

申请日：2004-01-23

申请人： Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Hao-Jan Chao ,  Hsin-Po Wang

发明人： Khader S. Abdel-Hafez ,  Xiaoqing Wen ,  Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Hao-Jan Chao ,  Hsin-Po Wang

IPC分类号： G01R31/3177 ,  G01R31/3181 ,  G01R31/3185

CPC分类号： G01R31/318572 ,  G01R31/31705 ,  G01R31/318591

摘要： A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations. Computer-aided design (CAD) methods are then proposed to automatically synthesize the output-mask controller 301, output-mask network 304, input chain-mask controller and input-mask network, and to further generate test patterns according to the synthesized scan-based integrated circuit.

摘要翻译： 一种用于基于扫描的集成电路的调试，诊断和/或产量改进的方法和装置，其中嵌入在扫描核心303中的扫描链没有外部访问，例如当它们被图案发生器302和模式压缩器包围时的情况 305，使用DFT（设计为测试）技术，如Logic BIST（内置自检）或压缩扫描。 本发明包括一个输出屏蔽控制器301和一个输出屏蔽网络304，以允许设计者掩蔽所选择的扫描单元311在选定的模式压实器305中被压缩。 本发明还包括输入链掩模控制器和输入掩模网络，用于将恒定逻辑值驱动到所选扫描链的扫描链输入中，以允许设计者从扫描链保持时间违规恢复。 然后提出了计算机辅助设计（CAD）方法来自动合成输出掩模控制器301，输出掩模网络304，输入链掩模控制器和输入掩模网络，并根据合成的扫描 - 基于集成电路。

公开(公告)号：US06957403B2

公开(公告)日：2005-10-18

申请号：US10108238

申请日：2002-03-28

申请人： Laung-Terng Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-P Wang

发明人： Laung-Terng Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-P Wang

IPC分类号： G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F17/50 ,  G06F19/00

CPC分类号： G06F17/505 ,  G01R31/31704 ,  G01R31/318314 ,  G01R31/318364 ,  G01R31/318583 ,  G01R31/318594 ,  G06F17/5022 ,  G06F17/5027 ,  G06F17/5045 ,  G06F2217/14

摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

摘要翻译： 一种在寄存器传输级（RTL）下自动扫描合成的方法和系统。 该方法和系统将产生在RTL建模的扫描HDL代码，用于在RTL建模的集成电路。 该方法和系统包括执行RTL可测试性分析，时钟域最小化，扫描选择，测试点选择，扫描修复和测试点插入，扫描替换和扫描拼接，扫描提取，交互式扫描调试，交互式扫描修复的计算机实现步骤 和冲洗/随机测试台生成。 此外，本发明还包括通过逐个模块执行扫描合成然后将这些扫描的模块拼接在一起的层次扫描合成的方法和系统。 本发明还包括将扫描HDL码与其他测试（DFT）HDL码进行集成和验证，包括边界扫描和逻辑BIST（内置自检）。

公开(公告)号：US06954887B2

公开(公告)日：2005-10-11

申请号：US10101517

申请日：2002-03-20

申请人： Laung-Terng (L.-T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

发明人： Laung-Terng (L.-T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.