公开(公告)号：US06284596B1

公开(公告)日：2001-09-04

申请号：US09213453

申请日：1998-12-17

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned. Hence, with this method, salicidation and self-aligned contact techniques can be used not only on the same VLSI and ULSI chips having both peripheral logic devices and memory devices, but also in memory devices themselves.

摘要翻译： 公开了一种用于形成具有盐化控制栅极和自对准触点的分离栅极闪存单元的方法。 通常用单栅极器件（例如逻辑器件）执行致敏。 在分支栅极中，其中控制栅极与中间栅极氧化物层覆盖浮置栅极，因为它们的位置与浮置栅极的位置处于不同的水平位置，因此在控制栅极上形成自对准硅化物是常规的不相容的。 此外，通常使用的氧化物间隔物在应用于存储单元时是不充分的。 在本发明中显示，通过在控制栅极上明智地使用另外的氮化物/氧化物层，现在可以有效地使用氧化物间隔物来描绘控制栅上可被硅化并且自对准的区域。 因此，利用这种方法，不仅可以使用具有外围逻辑器件和存储器件的同一VLSI和ULSI芯片，而且可以用于存储器件本身中，可以使用水化和自对准接触技术。

公开(公告)号：US06204126B1

公开(公告)日：2001-03-20

申请号：US09506930

申请日：2000-02-18

申请人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage. The tip substantially decreases the coupling ratio of the floating gate to the word line for fast erasing speed, while at the same time increasing the coupling of the source to the floating gate with the attendant increase in the programming speed of the split gate flash memory cell.

摘要翻译： 公开了一种用于形成分离栅闪存单元的方法，其中单元的浮置栅极自对准到隔离，源极和字线。 还公开了提供可能的电池的最大收缩率的多自对准结构。 通过首先在形成沟槽隔离的同时首先定义浮栅，然后通过使用氮化物层作为硬掩模来代替传统的多晶氧体来将源自对准到浮栅来实现多自对准 ，并最终形成多晶硅间隔物以将字线对准浮动栅极。 此外，通过使用“微笑效果”，薄的浮动门用于形成薄而尖的多头尖端。 尖端大大降低了浮动栅极与字线的耦合比，以实现快速擦除速度，同时增加了源极与浮栅的耦合，伴随着分流栅闪存单元的编程速度的增加 。

公开(公告)号：US06479859B2

公开(公告)日：2002-11-12

申请号：US09777303

申请日：2001-02-06

申请人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Tai-Fen Lin ,  Wen-Ting Chu ,  Chuang-Ke Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage. The tip substantially decreases the coupling ratio of the floating gate to the word line for fast erasing speed, while at the same time increasing the coupling of the source to the floating gate with the attendant increase in the programming speed of the split gate flash memory cell.

摘要翻译： 公开了一种用于形成分离栅闪存单元的方法，其中单元的浮置栅极自对准到隔离，源极和字线。 还公开了提供可能的电池的最大收缩率的多自对准结构。 通过首先在形成沟槽隔离的同时首先定义浮栅，然后通过使用氮化物层作为硬掩模来代替传统的多晶氧体来将源自对准到浮栅来实现多自对准 ，并最终形成多晶硅间隔物以将字线对准浮动栅极。 此外，通过使用“微笑效果”，薄的浮动门用于形成薄而尖的多头尖端。 尖端大大降低了浮动栅极与字线的耦合比，以实现快速擦除速度，同时增加了源极与浮栅的耦合，伴随着分流栅闪存单元的编程速度的增加 。

公开(公告)号：US06559501B2

公开(公告)日：2003-05-06

申请号：US09850639

申请日：2001-05-07

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned. Hence, with this method, salicidation and self-aligned contact techniques can be used not only on the same VLSI and ULSI chips having both peripheral logic devices and memory devices, but also in memory devices themselves.

摘要翻译： 公开了一种用于形成具有盐化控制栅极和自对准触点的分离栅极闪存单元的方法。 通常用单栅极器件（例如逻辑器件）执行致敏。 在分支栅极中，其中控制栅极与中间栅极氧化物层覆盖浮置栅极，因为它们的位置与浮置栅极的位置处于不同的水平位置，因此在控制栅极上形成自对准硅化物是常规的不相容的。 此外，通常使用的氧化物间隔物在应用于存储单元时是不充分的。 在本发明中显示，通过在控制栅极上明智地使用另外的氮化物/氧化物层，现在可以有效地使用氧化物间隔物来描绘控制栅上可被硅化并且自对准的区域。 因此，利用这种方法，不仅可以使用具有外围逻辑器件和存储器件的同一VLSI和ULSI芯片，而且可以用于存储器件本身中，可以使用水化和自对准接触技术。

公开(公告)号：US06455887B1

公开(公告)日：2002-09-24

申请号：US09320754

申请日：1999-05-27

申请人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

发明人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/115 ,  H01L29/7885

摘要： An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.

摘要翻译： FET半导体器件包括形成在衬底中的N区和P区，其中N区与P区并置，具有N区和P区之​​间的界面，并且N区中的第一通道 - 区域和P区域中的第二个通道。 N +漏极区域位于P区域中第一通道一侧的界面附近。 P +漏极区域位于N区域中第二通道一侧的界面附近。 N +源极区域与第一通道的与P区域中的界面相反。 P +源极区域与N区域中的界面在第一通道的相对侧。 宽栅电极EEPROM堆叠桥接N区和P区中的沟道。 堆叠包括隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极。 在与栅电极堆叠自对准的P区的表面中形成N +漏极区。 在与栅极电极堆叠自对准的N区域的表面中形成P +漏极区域。

公开(公告)号：US6060360A

公开(公告)日：2000-05-09

申请号：US843183

申请日：1997-04-14

申请人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Juang-Ke Yeh

发明人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Juang-Ke Yeh

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.

摘要翻译： 在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。 具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅 宽度。 在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。 控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。 将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。 源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

公开(公告)号：US5933732A

公开(公告)日：1999-08-03

申请号：US851563

申请日：1997-05-07

申请人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

发明人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Jian-Hsing Lee

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/115 ,  H01L29/7885

摘要： An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.

摘要翻译： FET半导体器件包括形成在衬底中的N区和P区，其中N区与P区并置，具有N区和P区之​​间的界面，并且N区中的第一通道 - 区域和P区域中的第二个通道。 N +漏极区域位于P区域中第一通道一侧的界面附近。 P +漏极区域位于N区域中第二通道一侧的界面附近。 N +源极区域与第一通道的与P区域中的界面相反。 P +源极区域与N区域中的界面在第一通道的相对侧。 宽栅电极EEPROM堆叠桥接N区和P区中的沟道。 堆叠包括隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极。 在与栅电极堆叠自对准的P区的表面中形成N +漏极区。 在与栅极电极堆叠自对准的N区域的表面中形成P +漏极区域。

公开(公告)号：US06509603B2

公开(公告)日：2003-01-21

申请号：US09818296

申请日：2001-03-27

申请人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Juang-Ke Yeh

发明人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Juang-Ke Yeh

IPC分类号： H01L29788

CPC分类号： H01L29/42324 ,  H01L29/7885

摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.

摘要翻译： 在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。 具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅 宽度。 在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。 控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。 将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。 源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

公开(公告)号：US06246089B1

公开(公告)日：2001-06-12

申请号：US09524518

申请日：2000-03-13

申请人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Juang-Ke Yeh

发明人： Yai-Fen Lin ,  Shiou-Hann Liaw ,  Di-Son Kuo ,  Juang-Ke Yeh

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.

摘要翻译： 在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。 具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅 宽度。 在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。 控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。 将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。 源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

公开(公告)号：US5970341A

公开(公告)日：1999-10-19

申请号：US988772

申请日：1997-12-11

申请人： Chrong-Jung Lin ,  Chia-Ta Hsieh ,  Jong Chen ,  Di-Son Kuo

发明人： Chrong-Jung Lin ,  Chia-Ta Hsieh ,  Jong Chen ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole. Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.

摘要翻译： 通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。 在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。 在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。 形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。 衬底中的源极/漏极区域与浮栅电极层自对准。 通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图。 在其中形成控制门孔。 在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。 在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。