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61.发明授权
公开(公告)号：US3872431A
公开(公告)日：1975-03-18
申请号：US42302573
申请日：1973-12-10
IPC分类号： G11B27/36
CPC分类号： H03M13/00
摘要： A plurality of binary-to-decimal converters, logic gates and inverters provide a signal to a first output terminal when at least one error occurs in a data character, provide a signal to a second output terminal when only one error occurs in the character and provide a signal to a third output terminal when at least two errors occur in the character.
摘要翻译： 当在数据字符中发生至少一个错误时，多个二进制到十进制转换器，逻辑门和反相器向第一输出端提供信号，当在字符中仅发生一个错误时，向第二输出端提供信号，以及 当字符中发生至少两个错误时，向第三输出端提供信号。
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公开(公告)号：US3866183A
公开(公告)日：1975-02-11
申请号：US39335873
申请日：1973-08-31
发明人： LANGE RONALD E
CPC分类号： G06F12/0864
摘要： A communications control apparatus prepares for the generation of an interrupt signal along with appropriate address signals to retrieve data information from the main memory store upon the request from the central processor. During preparation time, a tag directory is searched for an indication that the data information required is presently in the cache store. If a comparison is made, a match signal is generated to prevent the generation of the interrupt signal. The communications control apparatus addresses the cache store to retrieve the data information for use by the processor.
摘要翻译： 通信控制装置准备产生中断信号以及适当的地址信号，以便在来自中央处理器的请求时从主存储器存储器检索数据信息。 在准备时间期间，搜索标签目录以指示所需的数据信息当前在高速缓存存储器中。 如果进行比较，则产生匹配信号以防止产生中断信号。 通信控制装置对高速缓存存储器进行寻址以检索由处理器使用的数据信息。
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63.发明授权D.c. motor speed control system through phase control and phase locking circuit 失效直流电机速度控制系统通过相位控制和相位锁定电路
公开(公告)号：US3858100A
公开(公告)日：1974-12-31
申请号：US35624073
申请日：1973-05-01
发明人： BUSSI G , SCHIAPARELLI A
CPC分类号： H02P7/2913 , H02P23/186 , Y10S388/933
摘要： A digital phase control adjustment system is provided for a d.c. motor which finds particular utility in applications where fast start and stop operations of the motor are required. The pulses forming a reference signal and those forming a variable signal are stored sequentially in a shift register and when the shift register is alternately storing ones and zeros, the pulses of the two signals are in alternate sequence for a certain number of periods, indicating that the motor speed is near the intended value.
摘要翻译： 提供数字相位控制调整系统，用于直流 在需要电动机快速启动和停止操作的应用中，它具有特殊的用途。 形成参考信号的脉冲和形成可变信号的脉冲顺序地存储在移位寄存器中，并且当移位寄存器交替地存储1和0时，两个信号的脉冲在一定数量的周期内是交替的，表明 电机转速接近预期值。
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64.发明授权Series-parallel dual switching regulator for use with a variety of line voltages 失效系列并联双开关稳压器，具有多种线路电压
公开(公告)号：US3846695A
公开(公告)日：1974-11-05
申请号：US35799673
申请日：1973-05-07
CPC分类号： H02M3/3155 , H02M1/10 , Y10T307/653
摘要： The power section of the switching regulator is divided into two identical parts. The two parts may be connected in series when a high value of power line voltage is used. The two parts are connected in parallel when a lower value of power line voltage is used. The same value of regulated output voltage may be obtained with either the series or the parallel connection.
摘要翻译： 开关稳压器的功率部分分为两个相同的部分。 当使用高电力线电压时，两个部分可以串联连接。 当使用较低的电力线电压值时，两个部分并联连接。 可以通过串联或并联连接获得相同的稳压输出电压值。
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公开(公告)号：US3845474A
公开(公告)日：1974-10-29
申请号：US41308973
申请日：1973-11-05
CPC分类号： G06F12/0808
摘要： In a multiprocessor data processing system, all processors must have access to certain communications tables stored in the main memory shared by the processors. Each processor has a cache store embedded within for its individual use. A cache store in one processor might contain data from the communication tables which is obsoleted by operations of a second processor. The cache store clearing apparatus invalidates its data information any time its processor accesses the communication tables. The cache store is cleared by resetting tag directory indicators, a round robin counter and a column full flag, for each column in a four level set associative tag directory to the cache store. The data in the cache store need not be cleared. Using the four level set associative tag directory permits the data information in the cache store to be invalidated by a 16 pulse burst of signals for 1K words of cache store directed to the tag directory indicators.
摘要翻译： 在多处理器数据处理系统中，所有处理器必须能够访问由处理器共享的存储在主存储器中的某些通信表。 每个处理器都有一个缓存存储器，用于单独使用。 一个处理器中的高速缓存存储器可以包含来自通信表的数据，这些数据被第二处理器的操作废弃。 高速缓存存储清除装置在其处理器访问通信表时，使其数据信息无效。 通过将四级组合关联标签目录中每列的标签目录指示符，循环计数器和列完整标志重置为缓存存储，可以清除缓存存储。 高速缓存存储中的数据不需要被清除。 使用四级集合关联标签目录允许高速缓存存储器中的数据信息被针对指向标签目录指示符的高速缓存存储器的1K字的16个脉冲突发信号无效。
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公开(公告)号：US3833888A
公开(公告)日：1974-09-03
申请号：US32951373
申请日：1973-02-05
发明人： JOHNSON A , STAFFORD J , CUCCIO A
CPC分类号： G06F9/4812 , G06F9/4818 , G06F13/122
摘要： A digital processor includes: a main read only memory store providing instruction and constant data signals; a random access memory store for storing variable data signals; an input/output port unit communicating with the terminal devices; an interrupt address generator controlling the interrupt priority for the terminal devices; an arithmetic and logical unit; an instruction decoding and execution unit controlled according to instructions in a fast access read only memory store address controlled by the instruction signals in the main read only memory store for controlling the operations of the digital processor; and a group of working and general registers for buffer storage of digital signals. Interconnections between the units of the processor are through a single bidirectional data bus. Process steps control the operation of the processor according to an instruction format.
摘要翻译： 数字处理器包括：提供指令和恒定数据信号的主要只读存储器存储器; 用于存储可变数据信号的随机存取存储器; 与终端设备通信的输入/输出端口单元; 中断地址发生器控制终端设备的中断优先级; 算术和逻辑单元; 指令解码和执行单元，根据由主要只读存储器存储器中的指令信号控制的快速访问只读存储器存储器中的指令进行控制，用于控制数字处理器的操作; 以及一组用于缓冲存储数字信号的工作和通用寄存器。 处理器单元之间的互连通过单个双向数据总线。 处理步骤根据指令格式控制处理器的操作。
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67.发明授权
公开(公告)号：US3832684A
公开(公告)日：1974-08-27
申请号：US41149373
申请日：1973-10-31
发明人： BESENFELDER E
摘要： A plurality of JK flip-flops, inverters and logic gates provide error signals when errors in phase occur between the phase bits and the data bits of information retrieved from a magnetic medium. The apparatus also provides warning signals when data bits are missing from the retrieved information.
摘要翻译： 多个JK触发器，反相器和逻辑门在相位位和从磁介质检索的信息的数据位之间出现相位相位错误时提供错误信号。 当从检索到的信息中丢失数据位时，该装置还提供警告信号。
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公开(公告)号：US3829755A
公开(公告)日：1974-08-13
申请号：US34857173
申请日：1973-04-05
发明人： NOWELL J
CPC分类号： H02M3/3155
摘要： The sequencer employs a variable current source, a Schmidt trigger circuit, a one-shot, a pair of master-slave flip-flops and logic gates to provide pulses for operating a multiple switching regulator. A logic gate disables the sequencer to prevent the generation of pulses while a portion of the switching regulator is delivering current to an output terminal and thereby prevents possible damage to the switching regulator.
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69.发明授权
公开(公告)号：US3821716A
公开(公告)日：1974-06-28
申请号：US33453073
申请日：1973-03-05
发明人： GHAJAR P
CPC分类号： G11B20/18
摘要： Apparatus for detecting missing pulses in recovered NRZI encoded data. Positive and negative read signals are separated and applied to different error detecting circuits. Each error detecting circuit has a three stage, serial-transfer, shift register. The second stage output is connected to one circuit output terminal. The first and third stage outputs are applied to a conventional AND gate. The AND gate transmits an output pulse to the second circuit output terminal whenever the first and third stages contain logical ''''1''''s since the NRZI code dictates that an intermediate pulse of the opposite polarity must be missing. The circuit output terminals from both error detecting circuits are connected to the input of an OR gate.
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公开(公告)号：US3813652A
公开(公告)日：1974-05-28
申请号：US32358673
申请日：1973-01-15
CPC分类号： G06F12/0676
摘要： A system is disclosed in which an input binary address is transformed into a set of module select signals and a set of address signals whereby an aggregate of memory modules, each of which may contain a different number of storage cells, are combined to form a memory assembly which has a fixed number of storage cells. The address transformation system uses signals taken from the individual modules which represent the number of memory cells contained therein.
摘要翻译： 公开了一种系统，其中输入二进制地址被变换成一组模块选择信号和一组地址信号，由此可以组合每个可以包含不同数量的存储单元的存储器模块的集合以形成存储器 具有固定数量的存储单元的组件。 地址转换系统使用从各个模块获取的信号，这些信号表示其中包含的存储器单元的数量。
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