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公开(公告)号：US3764920A
公开(公告)日：1973-10-09
申请号：US3764920D
申请日：1972-06-15
摘要： The asynchronous signal is complemented and directed to a latching logic circuit as the data input and the synchronous signal are directed to the clock input of the latching circuit. The latching circuit has built-in delays to reliably latch if the low or active portion of the asynchronous pulse occurs during the ''''window'''' or high portion of the synchronous signal. The latching circuit also includes a jamming circuit connected to its clock input whereby a low or disabled window time of the synchronous signal prevents a change in state by the latching circuit. A pulse delay circuit generates a sampling pulse a period of time after the window time to sample the output of the latching circuit.
摘要翻译： 当数据输入和同步信号被引导到锁存电路的时钟输入时，异步信号被补充并被引导到锁存逻辑电路。 如果异步脉冲的低或有效部分在同步信号的“窗口”或高部分期间发生，则锁存电路具有内部延迟以可靠地锁存。 锁存电路还包括连接到其时钟输入的干扰电路，由此同步信号的低或禁止的窗口时间防止锁存电路的状态改变。 脉冲延迟电路在窗口时间之后的一段时间内产生采样脉冲，以采样锁存电路的输出。
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公开(公告)号：US3818460A
公开(公告)日：1974-06-18
申请号：US31957572
申请日：1972-12-29
发明人： LEMESSURIER BEARD A , COULEUR J , RUTH R , LANGE R , MONTEE R
IPC分类号： G06F9/46 , G06F9/32 , G06F9/34 , G06F9/355 , G06F12/02 , G06F12/06 , G06F9/20 , G05B19/28 , G06F9/10
CPC分类号： G06F9/342 , G06F9/32 , G06F12/0623
摘要： An extended addressing mechanism is disclosed for a digital computer system in which absolute addresses are generated over a span which exceeds the address span that can be generated by the address field of the computer instructions. For user slave programs, the regular base address register is augmented by an extended base address register. For operating system master mode programs, two master base address registers are provided, one for general purpose address augmentation and the other for special accumulator load/store instructions. In order to enable transformation of effective addresses to absolute addresses, special addition logic and control logic are also provided and combined so that effective addresses are selectively augmented or not, without increasing the time for preparation of the absolute address.
摘要翻译： 公开了一种用于数字计算机系统的扩展寻址机制，其中绝对地址在超过可由计算机指令的地址字段产生的地址跨度的跨度上生成。 对于用户从站程序，常规基址寄存器由扩展基址寄存器增加。 对于操作系统主模式程序，提供两个主基地址寄存器，一个用于通用地址扩充，另一个用于特殊的累加器加载/存储指令。 为了实现有效地址到绝对地址的转换，特殊的附加逻辑和控制逻辑也被提供和组合，使得有效地址有选择地增加，而不增加准备绝对地址的时间。
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公开(公告)号：US3845474A
公开(公告)日：1974-10-29
申请号：US41308973
申请日：1973-11-05
CPC分类号： G06F12/0808
摘要： In a multiprocessor data processing system, all processors must have access to certain communications tables stored in the main memory shared by the processors. Each processor has a cache store embedded within for its individual use. A cache store in one processor might contain data from the communication tables which is obsoleted by operations of a second processor. The cache store clearing apparatus invalidates its data information any time its processor accesses the communication tables. The cache store is cleared by resetting tag directory indicators, a round robin counter and a column full flag, for each column in a four level set associative tag directory to the cache store. The data in the cache store need not be cleared. Using the four level set associative tag directory permits the data information in the cache store to be invalidated by a 16 pulse burst of signals for 1K words of cache store directed to the tag directory indicators.
摘要翻译： 在多处理器数据处理系统中，所有处理器必须能够访问由处理器共享的存储在主存储器中的某些通信表。 每个处理器都有一个缓存存储器，用于单独使用。 一个处理器中的高速缓存存储器可以包含来自通信表的数据，这些数据被第二处理器的操作废弃。 高速缓存存储清除装置在其处理器访问通信表时，使其数据信息无效。 通过将四级组合关联标签目录中每列的标签目录指示符，循环计数器和列完整标志重置为缓存存储，可以清除缓存存储。 高速缓存存储中的数据不需要被清除。 使用四级集合关联标签目录允许高速缓存存储器中的数据信息被针对指向标签目录指示符的高速缓存存储器的1K字的16个脉冲突发信号无效。
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