System and method for detecting multiple direct sequence spread spectrum signals using a multi-mode searcher
    61.
    发明授权
    System and method for detecting multiple direct sequence spread spectrum signals using a multi-mode searcher 有权
    使用多模式搜索器检测多个直接序列扩频信号的系统和方法

    公开(公告)号:US07474688B2

    公开(公告)日:2009-01-06

    申请号:US10651282

    申请日:2003-08-28

    CPC classification number: H04B1/708 H04B2201/70711 H04J13/0044 H04J13/12

    Abstract: System and method for detecting multiple direct sequence spread spectrum signals using a multi-mode searcher. A preferred embodiment comprises the specification of a hypothesis for a particular communications network. The hypothesis can then be used to generate a pseudo-random number (PN) sequence that is provided to a searcher. The searcher can then make adjustments to the PN sequence to bring the PN sequence to conformity with requirements of the particular communications network. The adjustment to the PN sequence permits the use of a multi-mode searcher to perform searches for signals of various communications networks with minimal hardware dedicated to each communications network.

    Abstract translation: 使用多模式搜索器检测多个直接序列扩频信号的系统和方法。 优选实施例包括对特定通信网络的假设的规定。 然后可以使用该假设来产生提供给搜索者的伪随机数(PN)序列。 然后,搜索者可以对PN序列进行调整,使PN序列符合特定通信网络的要求。 对PN序列的调整允许使用多模式搜索器以专用于每个通信网络的最小硬件来执行各种通信网络的信号的搜索。

    Architecture for joint detection hardware accelerator
    62.
    发明申请
    Architecture for joint detection hardware accelerator 有权
    联合检测硬件加速器架构

    公开(公告)号:US20080080468A1

    公开(公告)日:2008-04-03

    申请号:US11818055

    申请日:2007-06-12

    CPC classification number: H04B1/7105 H04B2201/70707 H04B2201/70711

    Abstract: A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

    Abstract translation: 联合检测系统被配置为执行接收信号的联合检测,并且包括联合检测加速器和主机处理器。 联合检测加速器可以包括用于存储输入数据值,中间结果和输出数据值的存储单元; 一个或多个计算单元,用于处理输入数据值和中间结果,并向存储器单元提供输出数据值; 控制器,用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。 计算单元可以包括复数乘法单元,简化复乘法累积单元和归一化浮点除法器。 存储器单元可以包括输入存储器,矩阵存储器,主存储器和输出存储器。

    Wireless communications systems and methods for virtual user based multiple user detection utilizing vector processor generated mapped cross-correlation matrices
    63.
    发明授权
    Wireless communications systems and methods for virtual user based multiple user detection utilizing vector processor generated mapped cross-correlation matrices 有权
    基于虚拟用户的多用户检测的无线通信系统和方法,利用向量处理器生成的映射互相关矩阵

    公开(公告)号:US07218668B2

    公开(公告)日:2007-05-15

    申请号:US10099546

    申请日:2002-03-14

    Abstract: The invention provides methods and apparatus for multiple user detection (MUD) processing that have application, for example, in improving the capacity CDMA and other wireless base stations. One aspect of the invention provides a multiprocessor, multiuser detection system for detecting user transmitted symbols in CDMA short-code spectrum waveforms. A first processing element generates a matrix (hereinafter, “gamma matrix”) that represents a correlation between a short-code associated with one user and those associated with one or more other users. A set of second processing elements generates, e.g., from the gamma matrix, a matrix (hereinafter, “R-matrix”) that represents cross-correlations among user waveforms based on their amplitudes and time lags. A third processing element produces estimates of the user transmitted symbols as a function of the R-matrix.

    Abstract translation: 本发明提供了用于多用户检测(MUD)处理的方法和装置,其具有例如在改进容量CDMA和其它无线基站中的应用。 本发明的一个方面提供一种用于在CDMA短码频谱波形中检测用户发送符号的多处理器,多用户检测系统。 第一处理元件生成表示与一个用户相关联的短码与与一个或多个其他用户相关联的短码之间的相关性的矩阵(以下称为“伽马矩阵”)。 一组第二处理元件例如从伽马矩阵生成基于它们的幅度和时间滞后的用户波形之间的互相关的矩阵(以下称为“R矩阵”)。 第三处理单元产生作为R矩阵的函数的用户发送符号的估计。

    Load balancing computational methods in a short-code spread-spectrum communications system
    65.
    发明授权
    Load balancing computational methods in a short-code spread-spectrum communications system 有权
    短码扩频通信系统中的负载均衡计算方法

    公开(公告)号:US07203221B2

    公开(公告)日:2007-04-10

    申请号:US10099916

    申请日:2002-03-14

    Applicant: John H. Oates

    Inventor: John H. Oates

    Abstract: The invention provides methods and apparatus for multiple user detection (MUD) processing that have application, for example, in improving the capacity CDMA and other wireless base stations. One aspect of the invention provides a multiprocessor, multiuser detection system for detecting user transmitted symbols in CDMA short-code spectrum waveforms. A first processing element generates a matrix (hereinafter, “gamma matrix”) that represents a correlation between a short-code associated with one user and those associated with one or more other users. A set of second processing elements generates, e.g., from the gamma matrix, a matrix (hereinafter, “R-matrix”) that represents cross-correlations among user waveforms based on their amplitudes and time lags. A third processing element produces estimates of the user transmitted symbols as a function of the R-matrix.

    Abstract translation: 本发明提供了用于多用户检测(MUD)处理的方法和装置,其具有例如在改进容量CDMA和其它无线基站中的应用。 本发明的一个方面提供一种用于在CDMA短码频谱波形中检测用户发送符号的多处理器,多用户检测系统。 第一处理元件生成表示与一个用户相关联的短码与与一个或多个其他用户相关联的短码之间的相关性的矩阵(以下称为“伽马矩阵”)。 一组第二处理元件例如从伽马矩阵生成基于它们的幅度和时间滞后的用户波形之间的互相关的矩阵(以下称为“R矩阵”)。 第三处理单元产生作为R矩阵的函数的用户发送符号的估计。

    Computational methods for use in a short-code spread-spectrum communications system
    66.
    发明授权
    Computational methods for use in a short-code spread-spectrum communications system 有权
    用于短码扩频通信系统的计算方法

    公开(公告)号:US07164706B2

    公开(公告)日:2007-01-16

    申请号:US10098628

    申请日:2002-03-14

    Applicant: John H. Oates

    Inventor: John H. Oates

    Abstract: The invention provides methods and apparatus for multiple user detection (MUD) processing that have application, for example, in improving the capacity CDMA and other wireless base stations. One aspect of the invention provides a multiprocessor, multiuser detection system for detecting user transmitted symbols in CDMA short-code spectrum waveforms. A first processing element generates a matrix (hereinafter, “gamma matrix”) that represents a correlation between a short-code associated with one user and those associated with one or more other users. A set of second processing elements generates, e.g., from the gamma matrix, a matrix (hereinafter, “R-matrix”) that represents cross-correlations among user waveforms based on their amplitudes and time lags. A third procesing element produces estimates of the user transmitted symbols as a function of the R-matrix.

    Abstract translation: 本发明提供了用于多用户检测(MUD)处理的方法和装置,其具有例如在改进容量CDMA和其它无线基站中的应用。 本发明的一个方面提供一种用于在CDMA短码频谱波形中检测用户发送符号的多处理器,多用户检测系统。 第一处理元件生成表示与一个用户相关联的短码与与一个或多个其他用户相关联的短码之间的相关性的矩阵(以下称为“伽马矩阵”)。 一组第二处理元件例如从伽马矩阵生成基于它们的幅度和时间滞后的用户波形之间的互相关的矩阵(以下称为“R矩阵”)。 第三处理元素产生用户传输符号作为R矩阵的函数的估计。

    Configurable all-digital coherent demodulator system for spread spectrum applications
    69.
    发明申请
    Configurable all-digital coherent demodulator system for spread spectrum applications 失效
    可配置的全数字相干解调器系统,用于扩频应用

    公开(公告)号:US20060104389A1

    公开(公告)日:2006-05-18

    申请号:US11317524

    申请日:2005-12-22

    Inventor: Ravi Subramanian

    Abstract: A configurable all-digital coherent demodulator system for spread spectrum digital communications is disclosed herein. The demodulator system includes an extended and long-code demodulator (ELCD) coupled to a traffic channel demodulator (TCD) and a parameter estimator (PE). The demodulator also includes a pilot assisted correction device (PACD) that is coupled to the PE and the TCD. The ELCD provides a code-demodulated signal to the TCD and the PE. In turn, the TCD provides a demodulated output data signal to the PE. The PACD corrects the phase error of the demodulated output data based on an error estimate that is fed forward from the PE. Accumulation operations in the ELCD, TCD, and PE are all programmable. Similarly, a phase delay in the PACD is also programmable to provide synchronization with the error estimate from the PE.

    Abstract translation: 本文公开了一种用于扩频数字通信的可配置全数字相干解调器系统。 解调器系统包括耦合到业务信道解调器(TCD)和参数估计器(PE)的扩展和长码解调器(ELCD)。 解调器还包括耦合到PE和TCD的导频辅助校正装置(PACD)。 ELCD向TCD和PE提供码解调信号。 反过来,TCD向PE提供解调的输出数据信号。 基于从PE馈送的误差估计,PACD校正解调输出数据的相位误差。 ELCD,TCD和PE中的累加操作都可编程。 类似地,PACD中的相位延迟也是可编程的,以提供与来自PE的误差估计的同步。

    Reduced complexity correlator for use in a code division multiple access spread spectrum receiver
    70.
    发明授权
    Reduced complexity correlator for use in a code division multiple access spread spectrum receiver 失效
    用于码分多址扩频接收机的复杂度降低相关器

    公开(公告)号:US07039134B1

    公开(公告)日:2006-05-02

    申请号:US10050968

    申请日:2002-01-22

    CPC classification number: H04B1/707 H04B1/7095 H04B1/7115 H04B2201/70711

    Abstract: A reduced complexity correlator that enables the re-use of the most complex portions of a correlator, namely the multiplier and adder. The correlator of the present invention is especially well-suited for use in CDMA and W-CDMA spread spectrum communication systems that require the use of numerous correlators in their operation. Multiple input samples, multiple codes and integration results are stored in shift registers and circularly shifted and clocked out at appropriate clock rates such that the multiplication and accumulation steps of the correlation process are synchronized.

    Abstract translation: 一种降低的复杂度相关器,其能够重新使用相关器的最复杂部分,即乘法器和加法器。 本发明的相关器特别适用于需要在其操作中使用大量相关器的CDMA和W-CDMA扩频通信系统。 多个输入样本,多个代码和积分结果存储在移位寄存器中,并以适当的时钟速率循环移位和计时,使得相关处理的乘法和累加步骤同步。

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