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    METHOD AND APPARATUS FOR DETERMINING PRESENCE OF USER'S HAND TREMOR OR INTENTIONAL MOTION
    71.
    发明申请
    METHOD AND APPARATUS FOR DETERMINING PRESENCE OF USER'S HAND TREMOR OR INTENTIONAL MOTION 有权
    用于确定用户手中存在或意外运动的方法和装置

    公开(公告)号：US20100316299A1

    公开(公告)日：2010-12-16

    申请号：US12814024

    申请日：2010-06-11

    Applicant: Dong-Hyuk LEE ,  Mu-Sik Kwon ,  Sang-Wook Oh ,  Seong-Taek Hwang

    Inventor： Dong-Hyuk LEE ,  Mu-Sik Kwon ,  Sang-Wook Oh ,  Seong-Taek Hwang

    IPC: G06K9/62

    CPC classification number: H04N5/23267 ,  G06T7/223 ,  H04N5/23248 ,  H04N5/23254

    Abstract: A method is provided for determining presence of a user's hand tremor or intentional motion during recognition of an image through photographing. Image sample blocks of a previous frame are detected by using an edge detecting method. A block distance between the detected image sample block of the previous frame and an estimated image sample block of a current frame is calculated. The calculated block distance is compared with a first threshold. The calculated block distance is compared with a second threshold when the calculated block distance is less than the first threshold.

    Abstract translation: 提供一种用于在通过拍摄识别图像期间确定用户的手颤或有意运动的存在的方法。 通过使用边缘检测方法检测先前帧的图像采样块。 计算前一帧的检测图像采样块与当前帧的估计图像采样块之间的块距离。 将计算的块距离与第一阈值进行比较。 当所计算的块距离小于第一阈值时，将计算出的块距离与第二阈值进行比较。

    Semiconductor memory device having refresh circuit and word line activating method therefor
    72.
    发明申请
    Semiconductor memory device having refresh circuit and word line activating method therefor 失效
    具有刷新电路和字线激活方法的半导体存储器件

    公开(公告)号：US20090296510A1

    公开(公告)日：2009-12-03

    申请号：US12453164

    申请日：2009-04-30

    Applicant: Dong-Hyuk Lee ,  Chi-Sung Oh

    Inventor： Dong-Hyuk Lee ,  Chi-Sung Oh

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C11/406 ,  G11C11/40618 ,  G11C11/4085

    Abstract: A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block.

    Abstract translation: 半导体存储器件包括具有至少一个存储体的存储单元阵列。 存储体被分成存储块，使得存储块具有块位置，该块位置包括在存储体的边缘处的至少一个边缘存储器块和至少一个非边缘存储器块。 每个存储块包括多个存储单元。 每个存储器单元与至少一个位线和至少一个字线相关联。 所述半导体存储器件包括刷新执行电路，所述刷新执行电路被配置为在所述边缘存储器块中的存储器单元的刷新操作期间一次一个地激活小于或等于数量的字线， 非边缘存储器块中的存储单元。

    Apparatus and method for supplying voltage in semiconductor device
    73.
    发明授权
    Apparatus and method for supplying voltage in semiconductor device 有权
    用于在半导体器件中提供电压的装置和方法

    公开(公告)号：US07616033B2

    公开(公告)日：2009-11-10

    申请号：US11521652

    申请日：2006-09-15

    Applicant: Dong-Hyuk Lee

    Inventor： Dong-Hyuk Lee

    IPC: H03L7/00

    CPC classification number: H03K5/08

    Abstract: For supplying voltage to at least one main current consuming unit, a voltage supply unit provides the voltage to the at least one main current consuming unit at a supply node. In addition, an auxiliary current consuming unit conducts auxiliary current from/to the supply node for at least a predetermined time period before the at least one main current consuming unit begins to conduct current. Thus, voltage overshoot is prevented at the supply node.

    Abstract translation: 为了向至少一个主电流消耗单元提供电压，电压供应单元将电压提供给供电节点处的至少一个主电流消耗单元。 另外，在至少一个主电流消耗单元开始进行电流之前，辅助电流消耗单元在至少预定时间段内从辅助电流节点传送辅助电流。 因此，在供电节点处防止电压过冲。

    Method, device, and system for preventing refresh starvation in shared memory bank
    74.
    发明申请
    Method, device, and system for preventing refresh starvation in shared memory bank 有权
    用于防止共享存储器中刷新不足的方法，设备和系统

    公开(公告)号：US20090106503A1

    公开(公告)日：2009-04-23

    申请号：US11977047

    申请日：2007-10-23

    Applicant: Dong-Hyuk Lee ,  Kyung-Woo Nam ,  Yong-Jun Kim ,  Jong-Wook Park ,  Chi-Sung Oh

    Inventor： Dong-Hyuk Lee ,  Kyung-Woo Nam ,  Yong-Jun Kim ,  Jong-Wook Park ,  Chi-Sung Oh

    IPC: G06F12/14

    CPC classification number: G11C11/406 ,  G11C7/1075 ,  G11C11/40603 ,  G11C11/40618

    Abstract: A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.

    Abstract translation: 多端口存储器件包括刷新寄存器和刷新控制器，用于防止存储器件的共享存储器单元中的刷新不足。 存储装置还包括共享对共享存储器单元的访问的多个端口。 刷新寄存器存储关于至少一个刷新命令的信息。 刷新控制器根据存储在刷新寄存器中的信息来确定是否在端口权限转换时激活内部刷新操作。

    Cochlear Implant
    75.
    发明申请
    Cochlear Implant 失效
    人工耳蜗

    公开(公告)号：US20090005836A1

    公开(公告)日：2009-01-01

    申请号：US12097751

    申请日：2007-06-25

    Applicant: Y. Jay Chang ,  Dong Hyuk Lee

    Inventor： Y. Jay Chang ,  Dong Hyuk Lee

    IPC: A61F11/04

    CPC classification number: A61N1/0541 ,  A61N1/36036

    Abstract: There is provided a cochlear implant for improving the hearing ability of a patient suffered from hearing impairment comprising an internal receiving unit implanted into the body, which comprises a receiving part for receiving external signal, an active electrode and a reference electrode, characterized in that the active electrode is constructed with a single electrode wire having different thickness in at least two different regions. The active electrode of the internal receiving unit is inserted into a space formed at between the mastoid bone and the ear canal skin and end of the active electrode is inserted into the scala tympani of the cochlea and directly stimulates spiral ganglion. The cochlear implant provides easier implantation into the body and improved hearing ability at a lower cost.

    Abstract translation: 提供了一种用于改善患有听力障碍的患者的听力能力的耳蜗植入体，其包括植入体内的内部接收单元，其包括用于接收外部信号的接收部分，有源电极和参考电极，其特征在于， 有源电极由在至少两个不同区域中具有不同厚度的单电极线构成。 将内部接收单元的活性电极插入形成在乳突骨和耳道皮肤之间的空间中，并且将活性电极的末端插入耳蜗的鼓膜鼓并直接刺激螺旋神经节。 耳蜗植入物更容易地植入身体并以更低的成本提高听力能力。

    MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE WITH HOST INTERFACE BETWEEN PROCESSORS
    77.
    发明申请
    MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE WITH HOST INTERFACE BETWEEN PROCESSORS 有权
    具有处理器之间主机接口的多路可访问半导体存储器件

    公开(公告)号：US20080077937A1

    公开(公告)日：2008-03-27

    申请号：US11829859

    申请日：2007-07-27

    Applicant: Yun-Hee SHIN ,  Han-Gu SOHN ,  Young-Min LEE ,  Dong-Hyuk LEE ,  Jong-Wook PARK ,  Ho-Cheol LEE ,  Mi-Jo KIM ,  Jung-Sik KIM ,  Chang-Ho LEE

    Inventor： Yun-Hee SHIN ,  Han-Gu SOHN ,  Young-Min LEE ,  Dong-Hyuk LEE ,  Jong-Wook PARK ,  Ho-Cheol LEE ,  Mi-Jo KIM ,  Jung-Sik KIM ,  Chang-Ho LEE

    IPC: G06F15/167 ,  G06F9/30

    CPC classification number: G11C7/1075 ,  G11C7/1012 ,  G11C11/4096

    Abstract: A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

    Abstract translation: 多路可及半导体存储器件提供处理器之间的接口功能。 存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径 响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

    SEMICONDUCTOR MEMORY DEVICE HAVING CONNECTED BIT LINES AND DATA SHIFT METHOD THEREOF
    80.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING CONNECTED BIT LINES AND DATA SHIFT METHOD THEREOF 有权
    具有连接位线的半导体存储器件及其数据移位方法

    公开(公告)号：US20070014181A1

    公开(公告)日：2007-01-18

    申请号：US11457050

    申请日：2006-07-12

    Applicant: Dong-Hyuk LEE

    Inventor： Dong-Hyuk LEE

    IPC: G11C8/00

    CPC classification number: G11C7/18 ,  G11C7/1006 ,  G11C7/12 ,  G11C2207/002

    Abstract: Provided is a semiconductor memory device having connected bit lines and a data shifting method thereof. An embodiment of the semiconductor memory device includes a plurality of memory cell blocks each including a plurality of bit lines and a plurality of word lines, a plurality of sense amplifier blocks respectively disposed between the memory cell blocks, wherein each sense amplifier block includes a plurality of sense amplifier circuits corresponding to the bit lines, and a plurality of switches. The switches connect bit lines not sharing a sense amplifier block among bit lines of adjacent memory cell blocks between which the sense amplifier block is disposed, in response to a shift signal. Therefore, in the semiconductor memory device and the data shift method thereof, it is possible to easily shift data stored in memory cells connected to an arbitrary word line to memory cells connected to another arbitrary word line.

    Abstract translation: 提供了具有连接的位线及其数据移位方法的半导体存储器件。 半导体存储器件的实施例包括多个存储单元块，每个存储单元块包括多个位线和多个字线，分别设置在存储单元块之间的多个读出放大器块，其中每个读出放大器块包括多个 对应于位线的读出放大器电路，以及多个开关。 这些开关响应于移位信号，连接在相邻的存储单元块的位线之间不共享读出放大器块的位线，其间设置有读出放大器块。 因此，在半导体存储器件及其数据移位方法中，可以容易地将连接到任意字线的存储单元中存储的数据移位到连接到另一任意字线的存储单元。

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