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    Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith
    71.
    发明申请
    Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith 审中-公开
    具有基于电阻的存储器阵列，读取和写入方法以及与其相关联的系统的半导体器件

    公开(公告)号：US20100131708A1

    公开(公告)日：2010-05-27

    申请号：US12292896

    申请日：2008-11-28

    申请人： Joon-Min Park ,  Kwang Jin Lee ,  Beak-Hyung Cho

    发明人： Joon-Min Park ,  Kwang Jin Lee ,  Beak-Hyung Cho

    IPC分类号： G06F12/00

    CPC分类号： G11C13/0069 ,  G11C15/046 ,  G11C2013/0076

    摘要： In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write address buffer configured to store a write address associated with each data stored in the write buffer. An output circuit is configured to selectively output one of data read from the non-volatile memory array and data from the write buffer. A by-pass control circuit is configured to control the output circuit based on whether an input read address matches a valid write address stored in the write address buffer. An invalidation unit is configured to invalidate an address stored in the write address buffer if the stored write address matches an input write address.

    摘要翻译： 在一个实施例中，半导体器件包括非易失性存储器单元阵列，被配置为存储被写入非易失性存储单元阵列的数据的写入缓冲器，以及写入地址缓冲器，被配置为存储与存储的每个数据相关联的写入地址 在写缓冲区。 输出电路被配置为选择性地输出从非易失性存储器阵列读取的数据和来自写入缓冲器的数据之一。 旁路控制电路被配置为基于输入读取地址是否匹配存储在写入地址缓冲器中的有效写入地址来控制输出电路。 如果所存储的写入地址与输入写入地址相匹配，则无效单元被配置为使存储在写入地址缓冲器中的地址无效。

    Semiconductor memory device and method for reducing cell activation during write operations
    74.
    发明申请
    Semiconductor memory device and method for reducing cell activation during write operations 有权
    用于在写入操作期间减少电池激活的半导体存储器件和方法

    公开(公告)号：US20080101131A1

    公开(公告)日：2008-05-01

    申请号：US11790146

    申请日：2007-04-24

    申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    IPC分类号： G11C7/06

    CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

    摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

    摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。