利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

95 条记录 (耗时 0.033 秒)

    Semiconductor memory device and method for reducing cell activation during write operations
    1.
    发明申请
    Semiconductor memory device and method for reducing cell activation during write operations 有权
    用于在写入操作期间减少电池激活的半导体存储器件和方法

    公开(公告)号：US20080101131A1

    公开(公告)日：2008-05-01

    申请号：US11790146

    申请日：2007-04-24

    申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    IPC分类号： G11C7/06

    CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

    摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

    摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

    Semiconductor memory device and method for reducing cell activation during write operations
    2.
    发明授权
    Semiconductor memory device and method for reducing cell activation during write operations 有权
    用于在写入操作期间减少电池激活的半导体存储器件和方法

    公开(公告)号：US07542356B2

    公开(公告)日：2009-06-02

    申请号：US11790146

    申请日：2007-04-24

    申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

    IPC分类号： G11C7/06

    CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

    摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

    摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

    Method of testing PRAM device
    3.
    发明授权
    Method of testing PRAM device 有权
    PRAM设备的测试方法

    公开(公告)号：US07751232B2

    公开(公告)日：2010-07-06

    申请号：US11953146

    申请日：2007-12-10

    申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

    发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

    IPC分类号： G11C11/00

    CPC分类号： G11C29/08 ,  G11C13/0004

    摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

    摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

    Method of testing PRAM device
    4.
    发明授权
    Method of testing PRAM device 有权
    PRAM设备的测试方法

    公开(公告)号：US07869271B2

    公开(公告)日：2011-01-11

    申请号：US12787571

    申请日：2010-05-26

    申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

    发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

    IPC分类号： G11C11/00

    CPC分类号： G11C29/08 ,  G11C13/0004

    摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

    摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。