公开(公告)号：US08245017B2

公开(公告)日：2012-08-14

申请号：US12481118

申请日：2009-06-09

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/30058 ,  G06F9/3867

摘要： A microprocessor includes a first branch condition state and a second branch condition state. The microprocessor also includes a conditional branch instruction of a first type that instructs the microprocessor to wait to correctly resolve the conditional branch instruction of the first type based on the first branch condition state until other instructions within the microprocessor that update the first branch condition state and that are older than the conditional branch instruction of the first type have updated the first branch condition state. A conditional branch instruction of a second type instructs the microprocessor to correctly resolve the conditional branch instruction of the second type based on the second branch condition state without regard to whether other instructions within the microprocessor that update the second branch condition state and that are older than the conditional branch instruction of the second type have yet updated the second branch condition state.

摘要翻译： 微处理器包括第一分支状态和第二分支状态。 微处理器还包括第一类型的条件转移指令，指示微处理器基于第一转移条件状态等待正确地解析第一类型的条件转移指令，直到微处理器内的其他指令更新第一分支状态和 比第一类型的条件分支指令更旧的第一分支条件状态。 第二类型的条件分支指令指示微处理器基于第二分支条件状态来正确地解析第二类型的条件分支指令，而不考虑微处理器内是否更新第二分支条件状态并且比第二分支状态更新的其它指令 第二类型的条件分支指令还更新了第二分支条件状态。

公开(公告)号：US08234543B2

公开(公告)日：2012-07-31

申请号：US12609207

申请日：2009-10-30

申请人： G. Glenn Henry ,  Charles John Holthaus ,  Terry Parks

发明人： G. Glenn Henry ,  Charles John Holthaus ,  Terry Parks

IPC分类号： G06F11/00

CPC分类号： G11C17/18 ,  G06F11/1048 ,  G11C2029/0411

摘要： A microprocessor includes control hardware that receives and stores control values and provides the control values to circuits of the microprocessor for controlling operation of the microprocessor. The microprocessor also includes a first plurality of fuses selectively blown collectively with a predetermined value, and a second plurality of fuses selectively blown collectively with an error correction value computed from the predetermined value collectively blown into the first plurality of fuses. In response to being reset, the microprocessor reads the first and second plurality of fuses, detects an error in the value read from the first plurality of fuses using the value read from the second plurality of fuses, corrects the value read from the first plurality of fuses back to the predetermined value using the value read from the second plurality of fuses, and uses the corrected predetermined value to write the control values into the control hardware.

摘要翻译： 微处理器包括控制硬件，其接收并存储控制值，并将控制值提供给微处理器的电路以控制微处理器的操作。 微处理器还包括以预定值一起共同选择性地熔断的第一组多个熔丝，以及第二多个熔丝，其以从共同吹制到第一组熔丝中的预定值计算的误差校正值一起共同选择性地吹制。 响应于复位，微处理器读取第一和第二多个保险丝，使用从第二多个保险丝读取的值检测从第一多个保险丝读取的值中的错误，校正从第一多个保险丝读取的值 使用从第二多个保险丝读取的值将保险丝恢复到预定值，并且使用校正的预定值将控制值写入控制硬件。

公开(公告)号：US08209763B2

公开(公告)日：2012-06-26

申请号：US12263221

申请日：2008-10-31

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F12/14

CPC分类号： G06F21/72 ,  G06F12/1408 ,  G06F21/12 ,  G06F21/14 ,  G06F21/554 ,  G06F21/70 ,  G06F21/71 ,  G06F21/73 ,  G06F21/74 ,  G06F21/75 ,  G06F21/82

摘要： An apparatus including a microprocessor and a secure non-volatile memory. The microprocessor is a single integrated circuit disposed on a single die, and executes non-secure application programs and a secure application program. The secure application program is executed in a secure execution mode. The non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-volatile enabled indicator register that is configured indicate whether the microprocessor is within the secure execution mode or a non-secure execution mode, where contents of the non-volatile enabled indicator register persist through power removal and reapplication to the microprocessor. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.

摘要翻译： 一种包括微处理器和安全非易失性存储器的装置。 微处理器是单个集成电路，设置在单个管芯上，并执行非安全应用程序和安全应用程序。 安全应用程序以安全执行模式执行。 通过系统总线从系统存储器访问非安全应用程序。 微处理器具有非易失性使能指示符寄存器，其被配置为指示微处理器是处于安全执行模式还是非安全执行模式，其中非易失性使能指示符寄存器的内容通过电力消除持续并重新应用于微处理器 。 安全非易失性存储器经由专用总线耦合到微处理器，并被配置为存储安全应用程序，其中微处理器和安全非易失性存储器之间的专用总线上的事务与系统总线和对应的系统隔离 微处理器内的总线资源。

公开(公告)号：US20120096282A1

公开(公告)日：2012-04-19

申请号：US13091487

申请日：2011-04-21

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC分类号： G06F21/00 ,  H04L9/00

CPC分类号： H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

摘要： A fetch unit (a) fetches a block of instruction data from an instruction cache of the microprocessor; (b) performs an XOR on the block with a data entity to generate plain text instruction data; and (c) provides the plain text instruction data to an instruction decode unit. In a first instance the block comprises encrypted instruction data and the data entity is a decryption key. In a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes. The time required to perform (a), (b), and (c) is the same in the first and second instances regardless of whether the block is encrypted or unencrypted. A decryption key generator selects first and second keys from a plurality of keys, rotates the first key, and adds/subtracts the rotated first key to/from the second key, all based on portions of the fetch address, to generate the decryption key.

摘要翻译： 提取单元（a）从微处理器的指令高速缓冲存储器获取指令数据块; （b）使用数据实体在块上执行异或以产生明文指令数据; 和（c）将明文指令数据提供给指令译码单元。 在第一种情况下，块包括加密指令数据，数据实体是解密密钥。 在第二种情况下，该块包括未加密的指令数据，并且数据实体为布尔零。 执行（a），（b）和（c）所需的时间在第一和第二实例中是相同的，而不管该块是加密还是未加密。 解密密钥生成器从多个密钥中选择第一和第二密钥，旋转第一密钥，并且基于获取地址的部分，将旋转后的第一密钥加到/从第二密钥中加减乘以产生解密密钥。

公开(公告)号：US08132023B2

公开(公告)日：2012-03-06

申请号：US12977809

申请日：2010-12-23

申请人： Thomas A. Crispin ,  G. Glenn Henry ,  Terry Parks

发明人： Thomas A. Crispin ,  G. Glenn Henry ,  Terry Parks

IPC分类号： G06F12/14 ,  G06F9/30 ,  H04L9/32 ,  H04K1/00

CPC分类号： H04L9/3239 ,  G06F9/30007 ,  G06F9/30065 ,  G06F9/30185 ,  G06F9/3895 ,  G06F21/64 ,  G06F21/72 ,  H04L9/0643 ,  H04L2209/125 ,  H04L2209/60

摘要： A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit, executing the one of the hash operations. The executing includes indicating whether the one of the hash operations has been interrupted by an interrupting event; first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.

摘要翻译： 一种用于执行散列操作的方法，包括：接收规定所述散列操作之一和多个散列算法之一的哈希指令; 将所述散列指令转换成第一多个微指令和第二多个微指令; 并且经由哈希单元执行所述散列操作之一。 所述执行包括指示所述散列操作中的一个是否已被中断事件中断; 首先在所述散列单元内执行所述第一多个微指令以产生输出数据; 第二执行x86整数单元内的第二多个微指令，与第一次执行一起执行以测试标志寄存器中的位，更新文本指针寄存器，以及在执行散列操作期间处理中断; 以及在允许待决中断进行之前将相应的中间散列值存储到存储器。

公开(公告)号：US20110296206A1

公开(公告)日：2011-12-01

申请号：US13091828

申请日：2011-04-21

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC分类号： G06F21/00

CPC分类号： H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

摘要： A branch target address cache (BTAC) caches history information associated with branch and switch key instructions previously executed by a microprocessor. The history information includes a target address and an identifier (index into a register file) for identifying key values associated with each of the previous branch and switch key instructions. A fetch unit receives from the BTAC a prediction that the fetch unit fetched a previous branch and switch key instruction and receives the target address and identifier associated with the fetched branch and switch key instruction. The fetch unit also fetches encrypted instruction data at the associated target address and decrypts (via XOR) the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction. If the BTAC predicts correctly, a pipeline flush normally associated with the branch and switch key instruction is avoided.

摘要翻译： 分支目标地址缓存（BTAC）缓存与微处理器先前执行的分支和切换密钥指令相关联的历史信息。 历史信息包括用于识别与先前分支和切换键指令中的每一个相关联的键值的目标地址和标识符（到寄存器文件的索引）。 获取单元从BTAC接收预取，该预测获取单元获取先前的分支并切换密钥指令，并接收与获取的分支和切换键指令相关联的目标地址和标识符。 提取单元还在相关联的目标地址处获取加密指令数据，并且响应于接收到预测，基于由标识符标识的键值来解密（通过XOR）获取的加密指令数据。 如果BTAC正确预测，则避免通常与分支和切换键指令相关联的流水线清除。

公开(公告)号：US08060755B2

公开(公告)日：2011-11-15

申请号：US10800983

申请日：2004-03-15

申请人： G. Glenn Henry ,  Thomas A. Crispin ,  Terry Parks

发明人： G. Glenn Henry ,  Thomas A. Crispin ,  Terry Parks

IPC分类号： G06F12/14 ,  G06F9/30 ,  H04L9/00 ,  H04L9/32 ,  H04K1/00

CPC分类号： H04L9/0631 ,  G06F9/30007 ,  H04L2209/125 ,  H04L2209/24

摘要： An apparatus and method for performing cryptographic operations within microprocessor. The apparatus includes an instruction register having a cryptographic instruction disposed therein, a keygen unit, and an execution unit. The cryptographic instruction is received by a microprocessor as part of an instruction flow executing on the microprocessor. The cryptographic instruction prescribes one of the cryptographic operations, and also prescribes that a user-generated key schedule be employed when executing the one of the cryptographic operations. The keygen unit is operatively coupled to the instruction register. The keygen unit directs the microprocessor to load the user-generated key schedule. The execution unit is operatively coupled to the keygen unit. The execution unit employs the user-generated key schedule to execute the one of the cryptographic operations. The execution unit includes a cryptography unit.

摘要翻译： 一种用于在微处理器内执行加密操作的装置和方法。 该装置包括其中设置有密码指令的指令寄存器，密钥单元和执行单元。 加密指令由微处理器接收，作为在微处理器上执行的指令流的一部分。 密码指令规定了一个加密操作，并且还规定了当执行一个加密操作时采用用户生成的密钥调度。 密钥单元可操作地耦合到指令寄存器。 keygen单元指示微处理器加载用户生成的密钥计划。 执行单元可操作地耦合到密钥发生单元。 执行单元使用用户生成的密钥调度来执行密码操作之一。 执行单元包括密码单元。

公开(公告)号：US20110142229A1

公开(公告)日：2011-06-16

申请号：US12977809

申请日：2010-12-23

申请人： Thomas A. Crispin ,  G. Glenn Henry ,  Terry Parks

发明人： Thomas A. Crispin ,  G. Glenn Henry ,  Terry Parks

IPC分类号： H04L9/28

CPC分类号： H04L9/3239 ,  G06F9/30007 ,  G06F9/30065 ,  G06F9/30185 ,  G06F9/3895 ,  G06F21/64 ,  G06F21/72 ,  H04L9/0643 ,  H04L2209/125 ,  H04L2209/60

摘要： A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit, executing the one of the hash operations. The executing includes indicating whether the one of the hash operations has been interrupted by an interrupting event; first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.

摘要翻译： 一种用于执行散列操作的方法，包括：接收规定所述散列操作之一和多个散列算法之一的哈希指令; 将所述散列指令转换成第一多个微指令和第二多个微指令; 并且经由哈希单元执行所述散列操作之一。 所述执行包括指示所述散列操作中的一个是否已被中断事件中断; 首先在所述散列单元内执行所述第一多个微指令以产生输出数据; 第二执行x86整数单元内的第二多个微指令，与第一次执行一起执行以测试标志寄存器中的位，更新文本指针寄存器，以及在执行散列操作期间处理中断; 以及在允许待决中断进行之前将相应的中间散列值存储到存储器。

公开(公告)号：US07917568B2

公开(公告)日：2011-03-29

申请号：US11781754

申请日：2007-07-23

申请人： G. Glenn Henry ,  Timothy A. Elliott ,  Terry Parks

发明人： G. Glenn Henry ,  Timothy A. Elliott ,  Terry Parks

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/78 ,  G06F9/30014 ,  G06F9/30145 ,  G06F9/30163

摘要： An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register stack register. The microprocessor multiplies the first two operands and adds the product to the third operand to generate a result. The result is stored into the third register and the first two operands are popped off the stack. In an alternate embodiment, the third operand is also implicitly specified as being stored in the register that is two registers below the top of stack register; the result is also stored therein. The instruction opcode value is in the x87 opcode range.

摘要翻译： 公开了x86架构微处理器的指令集中的x87融合乘法（FMA）指令。 FMA指令将两个因子操作数隐含地指定为x87 FPU寄存器堆栈的前两个操作数，并将第三个加数操作数明确指定为第三个x87 FPU寄存器堆栈寄存器。 微处理器乘以前两个操作数，并将产品添加到第三个操作数以生成结果。 结果存储在第三个寄存器中，前两个操作数从堆栈中弹出。 在替代实施例中，第三操作数也被隐含地指定为存储在堆栈寄存器顶部下面的两个寄存器的寄存器中; 结果也存储在其中。 指令操作码值在x87操作码范围内。

公开(公告)号：US20110035617A1

公开(公告)日：2011-02-10

申请号：US12719291

申请日：2010-03-08

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F11/07

CPC分类号： G06F11/10 ,  G06F11/2236

摘要： A microprocessor includes a first plurality of fuses, selectively blown with a predetermined value for provision to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, selectively blown with error detection information used to detect an error in the first plurality of fuses such that a blown fuse of the microprocessor returned a non-blown binary value. In response to a user program instruction, the microprocessor is configured to determine whether there is an error in the first plurality of fuses such that a blown fuse returned a non-blown binary value using the error detection information from the second plurality of fuses.

摘要翻译： 微处理器包括第一组多个保险丝，其被选择性地以预定值吹送，以供给微处理器的电路以控制微处理器的操作。 微处理器还包括第二多个保险丝，其选择性地吹制有用于检测第一多个保险丝中的错误的错误检测信息，使得微处理器的保险丝熔断器返回非发送的二进制值。 响应于用户程序指令，微处理器被配置为确定在第一多个保险丝中是否存在错误，使得熔丝熔丝使用来自第二多个保险丝的错误检测信息返回未熔二进制值。