公开(公告)号：US12124571B2

公开(公告)日：2024-10-22

申请号：US17590037

申请日：2022-02-01

申请人： Microsoft Technology Licensing, LLC

发明人： Benito Joseph Rodriguez ,  Nisha Susan John

IPC分类号： G06F21/55 ,  G06F21/75

CPC分类号： G06F21/552 ,  G06F21/75 ,  G06F2221/034

摘要： A system for detecting access to a security sensitive component on an electronic device includes a PCB-mounted connector that provides read/write access to a security sensitive component on the PCB. The system further includes a connector cap that mates with at least a portion of the connector and that includes circuitry that facilitates current flow across at least a portion of the PCB-mounted connector when the connector cap is mated with the PCB-mounted connector, When removed from the PCB-mounted connector, the current flow is disrupted. The system further includes an intrusion detection controller that monitors a voltage at a sampling point adjacent to detect removal of the connector cap and to generate an intrusion logfile entry in response.

公开(公告)号：US20240296253A1

公开(公告)日：2024-09-05

申请号：US18661060

申请日：2024-05-10

申请人： STMicroelectronics (Rousset) SAS

发明人： Francesco La Rosa

IPC分类号： G06F21/75 ,  G06F21/72 ,  G11C11/4096 ,  H01L27/088 ,  H03K19/17768

CPC分类号： G06F21/75 ,  G06F21/72 ,  G11C11/4096 ,  H01L27/0883 ,  H03K19/17768

摘要： An embodiment system comprises a physical unclonable function device, wherein the device comprises a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution, and a processing circuit configured to deliver, to an output interface of the device, a group of output data based on a reading of the effective threshold voltages of the state transistors of the memory cells of the first assembly.

公开(公告)号：US12008246B2

公开(公告)日：2024-06-11

申请号：US17023308

申请日：2020-09-16

申请人： Axiado Corporation

发明人： Axel K. Kloth

IPC分类号： G06F21/57 ,  G06F3/06 ,  G06F8/654 ,  G06F9/44 ,  G06F9/4401 ,  G06F21/12 ,  G06F21/54 ,  G06F21/60 ,  G06F21/64 ,  G06F21/72 ,  G06F21/75 ,  G06F21/79 ,  G06F21/82 ,  H04L9/08 ,  H04L9/14 ,  H04L9/32 ,  G06F21/10

CPC分类号： G06F3/0623 ,  G06F3/0655 ,  G06F3/0679 ,  G06F8/654 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4406 ,  G06F21/12 ,  G06F21/54 ,  G06F21/57 ,  G06F21/572 ,  G06F21/575 ,  G06F21/602 ,  G06F21/64 ,  G06F21/72 ,  G06F21/75 ,  G06F21/79 ,  G06F21/82 ,  H04L9/0861 ,  H04L9/088 ,  H04L9/0894 ,  H04L9/14 ,  H04L9/3278 ,  G06F21/107 ,  G06F2221/033 ,  G06F2221/034

摘要： Techniques in electronic systems, such as in systems including a processing chip and one or more external memory chips, provide improvements in one or more of system security, performance, cost, and efficiency. The processing chip includes immutable hardware enabled to securely boot one or more CPUs of the processing chip to execute code stored in a non-volatile one of the external memory chips, and to update the code. An update to the code is written to a portion of one of the external memory chips that is not accessible to the CPUs, and the immutable hardware copies the update to the non-volatile memory chip. The update is encrypted with a public portion of a key possessed by an entity sending the update, and a private portion of the key, used to decrypt code stored in the non-volatile memory chip, is unique to and solely possessed by the processing chip.

公开(公告)号：US20240169100A1

公开(公告)日：2024-05-23

申请号：US18179385

申请日：2023-03-07

申请人： Wenzhou University

发明人： Gang LI ,  Hui Li ,  Pengjun WANG ,  Xilong Shao ,  Hao Ye

IPC分类号： G06F21/75 ,  H04L9/32

CPC分类号： G06F21/75 ,  H04L9/3278

摘要： A machine learning attack resistant strong PUF with a dual-edge sampling function comprises switch units, a first arbiter and a second arbiter. The first arbiter is for determining a sequential order of delays at a rising edge of signals input to a first input terminal and a second input terminal of the first arbiter. The second arbiter is for determining a sequential order of delays at a falling edge of signals input to a first input terminal and a second input terminal of the second arbiter. Each switch unit is composed of eight MOS transistors. The strong PUF has a high capacity to resist machine learning attacks and small hardware expenditure through simple structural design of the switch units, realizing machine learning attack resistance and small hardware expenditure at the same time, and generating a large number of challenge response pairs through dual-edge sampling realized by the two arbiters.

公开(公告)号：US11875180B2

公开(公告)日：2024-01-16

申请号：US17880539

申请日：2022-08-03

申请人： Dover Microsystems, Inc.

发明人： Steven Milburn ,  Gregory T. Sullivan

IPC分类号： G06F21/12 ,  G06F21/52 ,  G06F9/48 ,  G06F9/30 ,  G06F13/24 ,  G06F21/75

CPC分类号： G06F9/4812 ,  G06F9/3013 ,  G06F9/30043 ,  G06F13/24 ,  G06F21/75

摘要： Systems and methods for stalling a host processor. In some embodiments, the host processor may be caused to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction. The host processor may be prevented from completing the one or more selected transactions, to thereby stall the host processor.

公开(公告)号：US20240012946A1

公开(公告)日：2024-01-11

申请号：US18371045

申请日：2023-09-21

申请人： Arm Limited

发明人： Michael WEINER ,  Robert John HARRISON ,  Oded GOLOMBEK ,  Yoav Asher LEVY

IPC分类号： G06F21/75 ,  G06F30/398 ,  G06F30/396

CPC分类号： G06F21/75 ,  G06F30/398 ,  G06F30/396

摘要： Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

公开(公告)号：US20230385496A1

公开(公告)日：2023-11-30

申请号：US17664861

申请日：2022-05-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jinwook JUNG ,  Jennifer KAZDA ,  Schuyler ELDRIDGE ,  Peilin SONG ,  Gi-Joon NAM

IPC分类号： G06F30/3315 ,  G06F21/75

CPC分类号： G06F30/3315 ,  G06F21/75 ,  G06F2117/04

摘要： Embodiments are provided for providing enhanced protection of an integrated circuit in a computing system by a processor. A logic locking FSM component or a logic locking with RTL gating may be applied to a current design logic to enable and protect operations of an integrated circuit, where the current design logic remains unchanged. The operation of the integrated circuit may be activated based upon providing to the integrated circuit a correct key from the logic locking FSM component or the logic locking with RTL gating.

公开(公告)号：US11831777B2

公开(公告)日：2023-11-28

申请号：US17567388

申请日：2022-01-03

申请人： Ares Technologies, Inc.

发明人： Christian T. Wentz ,  Anna Lysyanskaya

IPC分类号： H04L9/00 ,  H04L9/32 ,  G06F21/75 ,  G06F21/62 ,  H04L9/08

CPC分类号： H04L9/3218 ,  G06F21/62 ,  G06F21/75 ,  H04L9/0866 ,  H04L9/3247 ,  H04L9/3278 ,  G06F2221/2143 ,  H04L2209/46

摘要： A secure computing hardware apparatus includes at least a secret generator module, the at least a secret generator module configured to generate a module-specific secret, and a device identifier circuit communicatively connected to the at least a secret generator, the device identifier circuit configured to produce at least an output comprising a secure proof of the module-specific secret. Secret generator module may implement one or more physically unclonable functions to generate the module-specific secret.

公开(公告)号：US20230317637A1

公开(公告)日：2023-10-05

申请号：US18206923

申请日：2023-06-07

申请人： STMicroelectronics (Rousset) SAS

发明人： Pascal FORNARA ,  Fabrice MARINET

IPC分类号： H01L23/00 ,  H01L29/788 ,  G06F21/75 ,  G06F21/79 ,  H01L23/522 ,  H10B41/35

CPC分类号： H01L23/573 ,  H01L29/7883 ,  H01L23/576 ,  G06F21/75 ,  G06F21/79 ,  H01L23/5223 ,  H10B41/35 ,  G06F21/87

摘要： An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

公开(公告)号：US11768611B2

公开(公告)日：2023-09-26

申请号：US17006717

申请日：2020-08-28

申请人： Axiado Corporation

发明人： Axel K. Kloth

IPC分类号： G06F3/06 ,  H04L9/08 ,  G06F21/57 ,  G06F8/654 ,  G06F21/12 ,  H04L9/14 ,  H04L9/32 ,  G06F9/4401 ,  G06F21/64 ,  G06F21/72 ,  G06F21/79 ,  G06F21/54 ,  G06F21/60 ,  G06F21/82 ,  G06F21/75

CPC分类号： G06F3/0623 ,  G06F3/0655 ,  G06F3/0679 ,  G06F8/654 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4406 ,  G06F21/12 ,  G06F21/54 ,  G06F21/57 ,  G06F21/572 ,  G06F21/575 ,  G06F21/602 ,  G06F21/64 ,  G06F21/72 ,  G06F21/75 ,  G06F21/79 ,  G06F21/82 ,  H04L9/088 ,  H04L9/0861 ,  H04L9/0894 ,  H04L9/14 ,  H04L9/3278 ,  G06F2221/033 ,  G06F2221/034 ,  G06F2221/0751 ,  G06F2221/0755

摘要： Techniques in electronic systems, such as in systems including a processing chip and one or more external memory chips, provide improvements in one or more of system security (such as intrusion and/or virus/malware prevention), performance, cost, and efficiency. For example, the processing chip includes at least one CPU and circuitry enabling the at least one CPU to securely boot from an external, non-volatile memory chip containing encrypted, executable code. The circuitry comprises immutable hardware to copy the executable code from the non-volatile memory to another external memory from which the at least one CPU is able to access it. The encryption uses a key created at a manufacturing time of and unique to the processing chip that is never CPU-accessible, forming a secure hardware association between the processing chip and the non-volatile memory chip.