公开(公告)号：US20190222229A1

公开(公告)日：2019-07-18

申请号：US16251373

申请日：2019-01-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Guido Montorsi ,  Sergio Benedetto ,  Yan Xin ,  Wei Lin ,  Min Yan

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1168 ,  H03M13/1185 ,  H03M13/635 ,  H03M13/6393 ,  H03M13/6527

Abstract: Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices. The Methods and devices use a LDPC matrix Hn of lifting factor Z. The LDPC matrix Hn comprises a plurality of submatrices, each submatrix having a size of Z×Z, and at least one submatrix has m1 diagonals of “1” m1 is an integer>=2.

公开(公告)号：US20170317868A1

公开(公告)日：2017-11-02

申请号：US15594185

申请日：2017-05-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wei Lin ,  Le Liu ,  Sergio Benedetto ,  Guido Montorsi ,  Weishan Lu

IPC: H04L27/26 ,  H04L12/801 ,  H04W72/04 ,  H04W84/12

CPC classification number: H04L27/2608 ,  H04L1/0042 ,  H04L1/0071 ,  H04L1/04 ,  H04L27/26 ,  H04L47/34 ,  H04W72/04 ,  H04W84/12

Abstract: Embodiments of the present disclosure provide an interleaving processing method and device in a WLAN system. The apparatus includes: a bit parsing unit, configured to allocate bits in a coded data stream to n sub resource block interleaving units according to a specific sequence, where n is a positive integer greater than 1, and a value of n is a quantity of resource blocks allocated to the user; and the sub resource block interleaving units, configured to perform discrete interleaving on input bits. According to the foregoing apparatus and method, system performance can be improved.

公开(公告)号：US08988932B2

公开(公告)日：2015-03-24

申请号：US14057863

申请日：2013-10-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Bingwu Ji ,  Yunming Zhou ,  Tanfu Zhao ,  Wei Lin

IPC: G11C11/00 ,  G11C11/413 ,  G11C11/419 ,  G11C8/18 ,  G11C11/418 ,  G11C11/41

CPC classification number: G11C11/413 ,  G11C8/18 ,  G11C11/41 ,  G11C11/418 ,  G11C11/419

Abstract: A timing processing method and a circuit for a synchronous SRAM are provided. The method includes: directly inputting an address signal to a wordline decoder for logic decoding; generating various signals by setting various devices in terms of timing; and performing sensitive amplification on data that is input by a memory cell array and is selected by a bitline, and then outputting the data, that is, generating a data output signal. The circuit for a synchronous SRAM includes: a wordline decoder, a timing generator, a wordline controller, a wordline pulse width generator, a memory cell array, and a sense amplifier.

Abstract translation: 提供了一种定时处理方法和用于同步SRAM的电路。 该方法包括：将地址信号直接输入到字线解码器进行逻辑解码; 通过在定时方面设定各种装置来产生各种信号; 对由存储单元阵列输入的数据执行敏感放大，并由位线选择，然后输出数据，即产生数据输出信号。 用于同步SRAM的电路包括：字线解码器，定时发生器，字线控制器，字线脉冲宽度发生器，存储单元阵列和读出放大器。