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71.发明申请公开(公告)号：US20220300607A1
公开(公告)日：2022-09-22
申请号：US17834446
申请日：2022-06-07
Applicant: Intel Corporation
Inventor： Marcio Juliato , Shabbir Ahmed , Manoj Sastry , Liuyang L. Yang , Vuk Lesi , Li Zhao
IPC: G06F21/55 , H04L9/40 , H04W4/48 , H04W4/38 , H04W12/122
Abstract: Methods and apparatus relating to a physics-based approach for attack detection and/or localization in closed-loop controls for autonomous vehicles are described. In an embodiment, multiple state estimators are used to compute a set of residuals to detect, classify, and/or localize attacks. This allows for determination of an attacker's location and the kind of attack being perpetrated. Other embodiments are also disclosed and claimed.
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公开(公告)号：US11424907B2
公开(公告)日：2022-08-23
申请号：US16911261
申请日：2020-06-24
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew H. Reinders , Joseph Friel , Avinash Laxmisha Varna , Manoj Sastry
Abstract: Embodiments are directed to countermeasures for side-channel attacks on protected sign and key exchange operations. An embodiment of storage mediums includes instructions for commencing a process including an elliptic curve scalar multiplication (ESM) operation including application of a secret scalar value; splitting the secret scalar value into two random scalar values; counting a number of leading ‘0’ bits in the scalar value and skipping the number of leading ‘0’ bits in processing; performing an ESM iteration for each bit of the secret scalar value beginning with a most significant ‘1’ bit of the scalar value including a Point Addition operation and a Point Double operation for each bit on randomized points; performing ESM operation dummy iterations equal to the number of leading ‘0’ bits; and returning an output result for the ESM operation.
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73.发明授权公开(公告)号：US11354406B2
公开(公告)日：2022-06-07
申请号：US16021409
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Marcio Juliato , Shabbir Ahmed , Manoj Sastry , Liuyang L. Yang , Vuk Lesi , Li Zhao
IPC: G06F21/55 , H04L9/40 , H04W4/48 , H04W4/38 , H04W12/122
Abstract: Methods and apparatus relating to a physics-based approach for attack detection and/or localization in closed-loop controls for autonomous vehicles are described. In an embodiment, multiple state estimators are used to compute a set of residuals to detect, classify, and/or localize attacks. This allows for determination of an attacker's location and the kind of attack being perpetrated. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20220131706A1
公开(公告)日：2022-04-28
申请号：US17568919
申请日：2022-01-05
Applicant: Intel Corporation
Inventor： Rafael Misoczki , Vikram Suresh , Santosh Ghosh , Manoj Sastry , Sanu Mathew , Raghavan Kumar
Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.
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公开(公告)号：US20220123949A1
公开(公告)日：2022-04-21
申请号：US17356048
申请日：2021-06-23
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj Sastry
Abstract: In one example an apparatus comprises one or more processors, and signature logic to receive a first plurality of state variables for use in a secure hash signature operation, compute a second plurality of operations from the first plurality of state variables to generate a corresponding second plurality of outputs, receive a signature key to be used in a secure hash operation, divide the signature key into a third plurality of chunks, implement, in a pseudo-random order, a fourth plurality of add operations to add the second plurality of outputs to the third plurality of chunks to update the first plurality of state variables. Other examples may be described.
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Patent Agency Ranking
76.发明申请公开(公告)号：US20220109558A1
公开(公告)日：2022-04-07
申请号：US17551525
申请日：2021-12-15
Applicant: Intel Corporation
Inventor： Vikram Suresh , Santosh Ghosh , Shalini Sharma , Eduard Lecha , Manoj Sastry , Xiaoyu Ruan , Sanu Mathew
IPC: H04L9/06
Abstract: In one example an apparatus comprises verification circuitry to store an object image in a computer readable memory external to an XMSS verifier circuitry and verify the object image by repeating operations to receive, in a local memory of the XMSS verifier circuitry, a fixed-sized block of data from the object image and process the fixed-sized block of data to compute the signature verification. Other examples may be described.
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公开(公告)号：US11277406B2
公开(公告)日：2022-03-15
申请号：US16455862
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Xiruo Liu , Rafael Misoczki , Santosh Ghosh , Manoj Sastry
Abstract: In one example a prover device comprises one or more processors, a computer-readable memory, and signature logic to store a first cryptographic representation of a first trust relationship between the prover device and a verifier device, the first cryptographic representation based on a pair of asymmetric hash-based multi-time signature keys, receive an attestation request message from the verifier device, the attestation request message comprising attestation data for the verifier device and a hash-based signature generated by the verifier device, and in response to the attestation request message, to verify the attestation data, verify the hash-based signature generated by the verifier device using a public key associated with the verifier device, generate an attestation reply message using a hash-based multi-time private signature key and send the attestation reply message to the verifier device. Other examples may be described.
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78.发明申请公开(公告)号：US20220014529A1
公开(公告)日：2022-01-13
申请号：US17484330
申请日：2021-09-24
Applicant: Intel Corporation
Inventor： Marcio Juliato , Javier Perez-Ramirez , Mikhail Galeev , Christopher Gutierrez , Dave Cavalcanti , Manoj Sastry , Vuk Lesi
Abstract: Systems and methods to detect attacks on the clocks of devices in time sensitive networks are described. Particularly, the disclosed systems and methods provide detection and mitigation of timing synchronization attacks based on pseudo-random numbers generated and used to select and authenticate timing of transmission of messages in protected transmission windows.
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公开(公告)号：US20220012331A1
公开(公告)日：2022-01-13
申请号：US17484689
申请日：2021-09-24
Applicant: Intel Corporation
Inventor： Shabbir Ahmed , Marcio Juliato , Vuk Lesi , Qian Wang , Manoj Sastry
Abstract: Systems, apparatuses, and methods to establish ground truth for an intrusion detection system in the presence of an attacker electronic control unit transmitting masqueraded messages on a communication bus, such as an in-vehicle network bus, are provided.
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公开(公告)号：US11223483B2
公开(公告)日：2022-01-11
申请号：US16456064
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Rafael Misoczki , Vikram Suresh , Santosh Ghosh , Manoj Sastry , Sanu Mathew , Raghavan Kumar
Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.
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