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公开(公告)号：US20230053981A1
公开(公告)日：2023-02-23
申请号：US17406186
申请日：2021-08-19
发明人： Steven J. Battle , Brian D. Barrick , Dung Q. Nguyen , Richard J. Eickemeyer , John B. Griswell, JR. , Balaram Sinharoy , Brian W. Thompto , Tu-An T. Nguyen
摘要： Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.
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公开(公告)号：US20230028929A1
公开(公告)日：2023-01-26
申请号：US17305734
申请日：2021-07-14
发明人： Brian D. Barrick , Bryan Lloyd , Dung Q. Nguyen , Brian W. Thompto , Edmund Joseph Gieske , John B. Griswell, JR.
摘要： A method for operation of a processor core is provided. First instruction data is consulted to determine whether a second instruction has execution data that matches the first instruction data. The first instruction data is from a first instruction. In response to determining that the second instruction has execution data that matches the first instruction data, prior data is copied into the second instruction. The first instruction depends on the prior data. After receiving an availability indication of the prior data, both the first instruction and the second instruction are woken for execution, without requiring execution of the first instruction before waking of the second instruction. The second instruction is executed by using the prior data as a skip of the first instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.
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公开(公告)号：US20220413868A1
公开(公告)日：2022-12-29
申请号：US17358183
申请日：2021-06-25
摘要： Embodiments for fast perfect issue of dependent instructions in a distributed issue queue system. Producer information of a producer instruction is inserted in a lookup entry in a lookup table, the lookup entry being allocated to a register. It is determined that the register corresponding to the lookup entry is a source for a dependent instruction. Responsive to storing the dependent instruction in an issue queue, the producer information is stored in a back-to-back entry of a back-to-back wakeup table, the back-to-back entry corresponding to the dependent instruction. The producer instruction is issued which causes the producer information of the producer instruction to be sent to the back-to-back wakeup table. It is determined that there is a match between the producer information and the back-to-back entry for the dependent instruction, and the dependent instruction is caused to issue based on the match.
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公开(公告)号：US11500642B2
公开(公告)日：2022-11-15
申请号：US17093757
申请日：2020-11-10
摘要： Provided is a method for assigning register tags to instructions at issue time. The method comprises receiving an instruction for execution by a microprocessor. The method further comprises dispatching the instruction to an issue queue without assigning a register tag to the instruction. The method further comprises determining that the instruction is ready to issue. In response to determining that the instruction is ready to issue, the method comprises assigning an available register tag to the instruction. The method further comprises issuing the instruction.
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公开(公告)号：US11194578B2
公开(公告)日：2021-12-07
申请号：US15987105
申请日：2018-05-23
发明人： Steven J. Battle , Brian D. Barrick , Joshua W. Bowman , Susan E. Eisen , Brandon Goddard , Cliff Kucharski , Dung Q. Nguyen , David S. Walder
摘要： A computer system, processor, and method for processing information is disclosed that includes at least one computer processor, a register file associated with the at least one processor, preferably a condition register that stores status information, the register file having multiple locations for storing data, multiple ports to write data to and read data from the register file. The system or processor includes an execution area, and the processor is configured to read from all the read ports in a first cycle, and to read from all the read ports in a second cycle. In an embodiment, the execution area includes a staging latch to store data from a first cycle read operation, and in an aspect the computer system is configured to combine the data stored in the staging latch during a first read cycle with the data read from the second cycle.
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公开(公告)号：US11182164B1
公开(公告)日：2021-11-23
申请号：US16936924
申请日：2020-07-23
摘要： Support for instruction fusion is provided. An indication whether an instruction is a paired instruction is received from an instruction decoder. Based on the indication, one dispatch slot or a paired dispatch slot is allocated in the instruction dispatcher queue. A mapper converts logical addresses of sources and targets of the instruction to physical addresses. Either one issue slot or a paired issue slot is allocated in an issue queue based on the indication from the instruction decoder. The instruction execution environment is loaded into the issue queue and issued to an execution unit.
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公开(公告)号：US20210342150A1
公开(公告)日：2021-11-04
申请号：US17120979
申请日：2020-12-14
发明人： Steven J. Battle , Kurt A. Feiste , Susan E. Eisen , Dung Q. Nguyen , Christian Gerhard Zoellin , Kent Li , Brian W. Thompto , Dhivya Jeganathan , Kenneth L. Ward , Brian D. Barrick
摘要： In at least one embodiment, a processor includes architected register file and non-architected register files for buffering operands. The processor additionally includes an instruction fetch unit that fetches instructions to be executed and at least one execution unit. The at least one execution unit is configured to execute a first class of instructions that access operands in the architected register file and a second class of instructions that access operands in the non-architected register file. The processor also includes a mapper circuit that assigns physical registers to the instructions for buffering of operands. The processor additionally includes a dispatch circuit configured, based on detection of an instruction in one of the first and second classes of instructions for which correct operands do not reside in a respective one of the architected and non-architected register files, to automatically initiate transfer of operands between the architected and non-architected register files.
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公开(公告)号：US10963380B2
公开(公告)日：2021-03-30
申请号：US16372997
申请日：2019-04-02
发明人： Gregory W. Alexander , Brian D. Barrick , Thomas W. Fox , Christian Jacobi , Anthony Saporito , Somin Song , Aaron Tsai
IPC分类号： G06F12/08 , G06F12/0811 , G06F12/0813 , G06F12/0855 , G06F9/30 , G06F12/0804 , G06F12/0875
摘要： A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.
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公开(公告)号：US20210089322A1
公开(公告)日：2021-03-25
申请号：US17109583
申请日：2020-12-02
发明人： Steven J. Battle , Salma Ayub , Brian D. Barrick , Joshua W. Bowman , Susan E. Eisen , Brandon Goddard , Christopher M. Mueller , Dung Q. Nguyen
摘要： A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.
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公开(公告)号：US10949213B2
公开(公告)日：2021-03-16
申请号：US16210349
申请日：2018-12-05
发明人： Steven J. Battle , Salma Ayub , Brian D. Barrick , Joshua W. Bowman , Susan E. Eisen , Brandon Goddard , Christopher M. Mueller , Dung Q. Nguyen
摘要： A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.
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