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    CACHE MANAGEMENT
    4.
    发明申请
    CACHE MANAGEMENT 审中-公开

    公开(公告)号：US20190370186A1

    公开(公告)日：2019-12-05

    申请号：US15996646

    申请日：2018-06-04

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Deanna P.D. Berger ,  CHRISTIAN JACOBI ,  Martin Recktenwald ,  Yossi Shapira ,  Aaron Tsai

    IPC分类号： G06F12/123 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/02

    摘要： A method, a computer system, and a computer program product to perform a directory lookup in a first level cache for requested cache line data. A first processor core can detect that the requested cache line data is not found in a plurality of sets of data in the first level cache and detect that existing cache line data stored in a least recently used data set stored in the first level cache is in an exclusive state, wherein the existing cache line data stored in the least recently used data set is to be overwritten by the requested cache line data retrieved from a second level cache. Furthermore, the first processor core can send a request for the requested cache line data and a physical address of the least recently used data set to the second level cache and execute additional instructions based on the first level cache and data retrieved from the second level cache.

    EFFICIENT POINTER LOAD AND FORMAT
    5.
    发明申请
    EFFICIENT POINTER LOAD AND FORMAT 审中-公开

    公开(公告)号：US20190018683A1

    公开(公告)日：2019-01-17

    申请号：US15848353

    申请日：2017-12-20

    申请人： International Business Machines Corporation

    发明人： Eyal Naor ,  Martin Recktenwald ,  Christian Zoellin ,  Aaron Tsai

    IPC分类号： G06F9/30 ,  G06F9/22

    摘要： Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.

    EFFICIENT POINTER LOAD AND FORMAT
    6.
    发明申请
    EFFICIENT POINTER LOAD AND FORMAT 审中-公开

    公开(公告)号：US20190018682A1

    公开(公告)日：2019-01-17

    申请号：US15848297

    申请日：2017-12-20

    申请人： International Business Machines Corporation

    发明人： Eyal Naor ,  Martin Recktenwald ,  Christian Zoellin ,  Aaron Tsai

    IPC分类号： G06F9/30 ,  G06F9/22

    CPC分类号： G06F9/30032 ,  G06F9/226

    摘要： Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.

    CACHE STRUCTURE USING A LOGICAL DIRECTORY
    7.
    发明申请
    CACHE STRUCTURE USING A LOGICAL DIRECTORY 审中-公开

    公开(公告)号：US20180365153A1

    公开(公告)日：2018-12-20

    申请号：US15844084

    申请日：2017-12-15

    申请人： International Business Machines Corporation

    发明人： Christian Jacobi ,  Ulrich Mayer ,  Martin Recktenwald ,  Anthony Saporito ,  Aaron Tsai

    IPC分类号： G06F12/0831 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/0811

    摘要： Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.