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公开(公告)号：US20230214218A1
公开(公告)日：2023-07-06
申请号：US17569951
申请日：2022-01-06
发明人： Steven J. Battle , Brian D. Barrick , Dung Q. Nguyen , Richard J. Eickemeyer , John B. Griswell, JR. , Balaram Sinharoy , Brian W. Thompto , Tu-An T. Nguyen
CPC分类号： G06F9/30058 , G06F9/30043 , G06F9/30021 , G06F9/3855 , G06F9/3842 , G06N5/04
摘要： A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.
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公开(公告)号：US20230077629A1
公开(公告)日：2023-03-16
申请号：US18051175
申请日：2022-10-31
摘要： Provided is a method for assigning register tags to instructions at issue time. The method comprises receiving an instruction for execution by a microprocessor. The method further comprises dispatching the instruction to an issue queue without assigning a register tag to the instruction. The method further comprises determining that the instruction is ready to issue. In response to determining that the instruction is ready to issue, the method comprises assigning an available register tag to the instruction. The method further comprises issuing the instruction.
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公开(公告)号：US11327757B2
公开(公告)日：2022-05-10
申请号：US17120979
申请日：2020-12-14
发明人： Steven J. Battle , Kurt A. Feiste , Susan E. Eisen , Dung Q. Nguyen , Christian Gerhard Zoellin , Kent Li , Brian W. Thompto , Dhivya Jeganathan , Kenneth L. Ward , Brian D. Barrick
IPC分类号： G06F9/30 , G06F9/38 , G06F12/02 , G06F12/0811 , G06F12/0862 , G06F12/1045
摘要： In at least one embodiment, a processor includes architected and non-architected register files for buffering operands. The processor additionally includes an instruction fetch unit that fetches instructions to be executed and at least one execution unit. The at least one execution unit is configured to execute a first class of instructions that access operands in the architected register file and a second class of instructions that access operands in the non-architected register file. The processor also includes a mapper circuit that assigns physical registers to the instructions for buffering of operands. The processor additionally includes a dispatch circuit configured, based on detection of an instruction in one of the first and second classes of instructions for which correct operands do not reside in a respective one of the architected and non-architected register files, to automatically initiate transfer of operands between the architected and non-architected register files.
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公开(公告)号：US11093282B2
公开(公告)日：2021-08-17
申请号：US16383775
申请日：2019-04-15
发明人： Brian D. Barrick , Steven J. Battle , Joshua W. Bowman , Cliff Kucharski , Hung Q. Le , Dung Q. Nguyen , David R. Terry
摘要： A non-limiting example of a computer-implemented method for file register writes using pointers includes, responsive to a dispatch instruction, storing, at a location in a history buffer, an instruction tag and first data associated with the instruction tag. The method further includes storing a pointer in an issue queue. The pointer points to the location in the history buffer. The method further includes performing a write back of second data using the pointer stored in the issue queue. The write back writes the second data into the location of the history buffer associated with the pointer.
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公开(公告)号：US11068267B2
公开(公告)日：2021-07-20
申请号：US16392722
申请日：2019-04-24
发明人： Steven J. Battle , Brandon Goddard , Dung Q. Nguyen , Joshua W. Bowman , Brian D. Barrick , Susan Eisen , Salma Ayub , Christopher M. Mueller
摘要： An aspect includes receiving a flush request at a processing unit that is in a current state defined by contents of registers in a register file. The processing unit includes a plurality of slices and the flush request includes an identifier of a previously issued instruction. The processing unit is restored to a previous state defined by contents of the registers in the register file prior to the previously issued instruction being issued. The restoring includes searching previous state buffers in at least two of the plurality of slices to locate data describing the contents of the registers in the register file prior to the previously issued instruction being issued. The restoring also includes combining the located data to generate results of the searching and updating the contents of the registers in the register file using a single port based at least in part on the results.
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公开(公告)号：US20210173649A1
公开(公告)日：2021-06-10
申请号：US16705362
申请日：2019-12-06
发明人： Steven J Battle , Brian D. Barrick , Susan E. Eisen , Andreas Wagner , Dung Q. Nguyen , Brian W. Thompto , Hung Q. Le , Kenneth L. Ward
摘要： A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number “N” of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.
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公开(公告)号：US10956158B2
公开(公告)日：2021-03-23
申请号：US16408749
申请日：2019-05-10
发明人： Steven J. Battle , Khandker N. Adeeb , Brian D. Barrick , Joshua W. Bowman , Thao T. Doan , Susan E. Eisen , Brandon Goddard , Dung Q. Nguyen
摘要： A method, processor and system for processing data is disclosed that includes evicting one or more evicted fields from a logical register mapper; receiving, by a history buffer, the one or more evicted fields from the logical register mapper; determining whether two or more of the evicted fields from the mapper qualify to be written to a single entry in the history buffer; and in response to the two or more evicted fields qualifying, writing the two or more qualifying evicted fields received from the mapper to a single entry in the qualified history buffer. The method, processor, and/or system further includes in an embodiment, remapping the one or more qualified evicted fields, and further, in response to the two or more evicted fields not qualifying to be written to a single entry in the history buffer, writing the two or more evicted fields to multiple history buffer entries.
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公开(公告)号：US10909034B2
公开(公告)日：2021-02-02
申请号：US15845757
申请日：2017-12-18
发明人： David R. Terry , Dung Q. Nguyen , Brian W. Thompto , Joshua W. Bowman , Steven J. Battle , Sundeep Chadha , Brian D. Barrick , Albert J. Van Norstrand, Jr.
IPC分类号： G06F12/0804
摘要： Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.
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公开(公告)号：US20200241931A1
公开(公告)日：2020-07-30
申请号：US16257259
申请日：2019-01-25
发明人： Steven J. Battle , Brandon R. Goddard , Dung Q. Nguyen , Joshua W. Bowman , Brian D. Barrick , Susan E. Eisen , David S. Walder , Cliff Kucharski
摘要： Recovering microprocessor logical register values by: partitioning a register mapper by logical register type; providing a plurality of recovery ports; assigning a logical register type to a recovery port; receiving a restore required instruction; and mapping SRB (save and restore buffer) values to the register mapper by logical register type.
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公开(公告)号：US20200183701A1
公开(公告)日：2020-06-11
申请号：US16210377
申请日：2018-12-05
发明人： Steven J. Battle , Khandker Nabil Adeeb , Brian D. Barrick , Joshua W. Bowman , Susan E. Eisen , Brandon Goddard , Jamory Hawkins , Dung Q. Nguyen
摘要： A computer system, processor, and method for processing information is disclosed that includes reading out a plurality of entries in a history buffer prior to initiating a flush recovery process; initiating the flush recovery process; determining which of the history buffer entries read out of the history buffer should be recovered; and sending information associated with the history buffer entries to be recovered to one or more history buffer recovery ports. In one or more embodiments, the history buffer entries are continually read out in response to a processor and history buffer entries read out from the history buffer are directed to a specific history buffer recovery port associated with a mapper of a specific logical register.
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