公开(公告)号：US20050251660A1

公开(公告)日：2005-11-10

申请号：US10840560

申请日：2004-05-06

申请人： Robert Bell ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  Jeffrey Stuecheli

发明人： Robert Bell ,  Thomas Capasso ,  Guy Guthrie ,  Hugh Shen ,  Jeffrey Stuecheli

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3824 ,  G06F9/3861

摘要： A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.

摘要翻译： 一种方法和处理器芯片设计，用于使得处理器核心能够在核心接收到存储队列已满的指示之后继续向商店队列发送存储操作。 处理器核心配置有推测存储逻辑，使得处理器核心能够在存储队列满信号被断言的同时继续发出存储操作。 投机发行的存储操作的副本放置在推测性存储缓冲区内。 核心等待来自存储队列的信号，指示存储操作被接受到存储队列中。 当存储队列中接受推测发出的存储操作时，该副本将从缓冲区中丢弃。 然而，当存储操作被拒绝时，推测存储逻辑在正常存储操作之前重新发布存储操作。

公开(公告)号：US20050193174A1

公开(公告)日：2005-09-01

申请号：US11041711

申请日：2005-01-22

申请人： Ravi Arimilli ,  Vicente Chung ,  Guy Guthrie ,  Jody Joyner

发明人： Ravi Arimilli ,  Vicente Chung ,  Guy Guthrie ,  Jody Joyner

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0831

摘要： A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference. One preference order is selected and the data is then retrieved from a cache line of the cache in the order selected.

摘要翻译： 一种用于向处理器通知所选择的数据传输顺序的处理器的方法。 该方法包括以下步骤：将系统组件经由数据总线耦合到处理器以实现数据传输，在系统组件逻辑处确定将数据发送到处理器的顺序，以及向数据总线发出与 数据，其中所选择的订单位向处理器提醒订单，并且以该顺序传送数据。 在优选实施例中，系统组件是高速缓存，并且该方法可以涉及在高速缓存处接收对来自处理器的读取地址/请求的排序的偏好。 高速缓存控制器或偏好顺序逻辑组件的偏好顺序逻辑通过将处理器偏好与其他偏好（包括高速缓存顺序偏好）进行比较来评估期望的顺序的偏好。 选择一个偏好顺序，然后以所选顺序从高速缓存的高速缓存行检索数据。

公开(公告)号：US5388223A

公开(公告)日：1995-02-07

申请号：US755474

申请日：1991-09-05

申请人： Guy Guthrie ,  Jeffery L. Swarts

发明人： Guy Guthrie ,  Jeffery L. Swarts

IPC分类号： G06F13/37 ,  H04L12/433 ,  G06F13/36

CPC分类号： G06F13/37 ,  H04L12/433

摘要： A 1-bit token ring arbitration architecture where a plurality of chips which require access to a shared bus are coupled together in a ring is described. Each chip receives an arbitration in signal from the preceding member of the ring which is used to receive the token. Each chip transmits an arbitration out signal to the following member of the ring to send the token to the following member. In the preferred embodiment, the token appears as a 1 cycle active low pulse. An error signal notifies all the bus participants that a ring error has been detected. Preferably, the number of cycles the error signal is held active, the more severe the error. A request of bus (ROB) signal notifies the chip holding the token that another bus member needs to use the bus. The ROB signal allows the current holder of the token to maintain control of the bus if it has further processing on the bus as long as no other bus member needs the bus. A Token Hold Timer may be included in a ring member which defines how long the member can hold on to the token after receiving notification on the ROB line that another bus participant wants the bus.

摘要翻译： 描述了需要访问共享总线的多个芯片以环形耦合在一起的1位令牌环仲裁架构。 每个芯片从用于接收令牌的环的前一成员的信号中接收仲裁。 每个芯片向环的下一个成员发送仲裁输出信号，以将令牌发送到下一个成员。 在优选实施例中，令牌显示为1个周期的有效低电平脉冲。 错误信号通知所有总线参与者已检测到环路错误。 优选地，误差信号保持有效的周期数，误差越严重。 总线（ROB）信号的请求通知保存令牌的芯片，另一个总线成员需要使用总线。 只要没有其他总线构件需要总线，ROB信号允许令牌的当前持有者在总线上进行进一步的处理来维持总线的控制。 令牌保持定时器可以包括在环成员中，该环成员定义了在ROB线上接收到另一个总线参与者想要总线的通知之后，成员可以持续多长时间。

公开(公告)号：US20060294309A1

公开(公告)日：2006-12-28

申请号：US11168715

申请日：2005-06-28

申请人： Guy Guthrie ,  Jeffrey Kellington ,  Kevin Reick ,  Hugh Shen

发明人： Guy Guthrie ,  Jeffrey Kellington ,  Kevin Reick ,  Hugh Shen

IPC分类号： G06F12/00

CPC分类号： G06F12/0802 ,  G06F12/0897

摘要： An efficient system for bootstrap loading scans cache lines into a cache store queue during a scan phase, and then transmits the cache lines from the cache store queue to a cache memory array during a functional phase. Scan circuitry stores a given cache line in a set of latches associated with one of a plurality of cache entries in the cache store queue, and passes the cache line from the latch set to the associated cache entry. The cache lines may be scanned from test software that is external to the computer system. Read/claim dispatch logic dispatches store instructions for the cache entries to read/claim machines which write the cache lines to the cache memory array without obtaining write permission, after the read/claim machines evaluate a mode bit which indicates that cache entries in the cache store queue are scanned cache lines. In the illustrative embodiment the cache memory is an L2 cache.

摘要翻译： 引导加载的有效系统在扫描阶段将高速缓存行扫描到高速缓存存储队列中，然后在功能阶段将高速缓存行从高速缓存存储队列发送到高速缓冲存储器阵列。 扫描电路将给定的高速缓存行存储在与高速缓存存储队列中的多个高速缓存条目之一相关联的一组锁存器中，并将高速缓存线从锁存器组传递到相关联的高速缓存条目。 高速缓存行可以从计算机系统外部的测试软件扫描。 阅读/权利要求调度逻辑调度高速缓存条目的存储指令以在读取/权利要求机器评估指示高速缓存中的高速缓存条目的模式位之后读取/声明将缓存行写入高速缓冲存储器阵列而不获得写入许可的机器 存储队列被扫描缓存行。 在说明性实施例中，高速缓存存储器是L2高速缓存。