公开(公告)号：US5379386A

公开(公告)日：1995-01-03

申请号：US101793

申请日：1993-08-02

申请人： Jeffery L. Swarts ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  Denis A. Smetana, Jr.

发明人： Jeffery L. Swarts ,  James S. Fields, Jr. ,  Guy L. Guthrie ,  Denis A. Smetana, Jr.

IPC分类号： G06F13/40 ,  G06F3/00

CPC分类号： G06F13/4027

摘要： A Micro Channel integrated circuit design capable of controlling high speed data and control transfers between a Micro Channel bus, a local processor, and a dedicated local data bus. The interface controller utilizes enhanced features of the Micro Channel and data buffering to achieve high speed data communications with various bit size Micro Channel devices. Queued commands are handled by flexibly programming the interface control operations. Interface control hardware increases the processing speed of data transfers by implementing performance critical functions of queuing in hardware. Extensive error checking and reporting and self-test give the interface controller advance functions as an input/output processor.

摘要翻译： 一种微通道集成电路设计，能够控制高速数据和控制微通道总线，本地处理器和专用本地数据总线之间的传输。 接口控制器利用微信道和数据缓冲的增强功能实现与各种位大小的微通道设备的高速数据通信。 排队的命令通过灵活编程接口控制操作来处理。 接口控制硬件通过实现硬件排队的性能关键功能来提高数据传输的处理速度。 广泛的错误检查和报告和自检给出了作为输入/输出处理器的接口控制器提前功能。

公开(公告)号：US5388223A

公开(公告)日：1995-02-07

申请号：US755474

申请日：1991-09-05

申请人： Guy Guthrie ,  Jeffery L. Swarts

发明人： Guy Guthrie ,  Jeffery L. Swarts

IPC分类号： G06F13/37 ,  H04L12/433 ,  G06F13/36

CPC分类号： G06F13/37 ,  H04L12/433

摘要： A 1-bit token ring arbitration architecture where a plurality of chips which require access to a shared bus are coupled together in a ring is described. Each chip receives an arbitration in signal from the preceding member of the ring which is used to receive the token. Each chip transmits an arbitration out signal to the following member of the ring to send the token to the following member. In the preferred embodiment, the token appears as a 1 cycle active low pulse. An error signal notifies all the bus participants that a ring error has been detected. Preferably, the number of cycles the error signal is held active, the more severe the error. A request of bus (ROB) signal notifies the chip holding the token that another bus member needs to use the bus. The ROB signal allows the current holder of the token to maintain control of the bus if it has further processing on the bus as long as no other bus member needs the bus. A Token Hold Timer may be included in a ring member which defines how long the member can hold on to the token after receiving notification on the ROB line that another bus participant wants the bus.

摘要翻译： 描述了需要访问共享总线的多个芯片以环形耦合在一起的1位令牌环仲裁架构。 每个芯片从用于接收令牌的环的前一成员的信号中接收仲裁。 每个芯片向环的下一个成员发送仲裁输出信号，以将令牌发送到下一个成员。 在优选实施例中，令牌显示为1个周期的有效低电平脉冲。 错误信号通知所有总线参与者已检测到环路错误。 优选地，误差信号保持有效的周期数，误差越严重。 总线（ROB）信号的请求通知保存令牌的芯片，另一个总线成员需要使用总线。 只要没有其他总线构件需要总线，ROB信号允许令牌的当前持有者在总线上进行进一步的处理来维持总线的控制。 令牌保持定时器可以包括在环成员中，该环成员定义了在ROB线上接收到另一个总线参与者想要总线的通知之后，成员可以持续多长时间。

公开(公告)号：US5418930A

公开(公告)日：1995-05-23

申请号：US755476

申请日：1991-09-05

申请人： Jeffery L. Swarts

发明人： Jeffery L. Swarts

IPC分类号： G06F13/00 ,  G06F11/267 ,  G06F13/42 ,  H04L29/06

CPC分类号： G06F13/4217 ,  G06F11/221

摘要： An Asynchronous Communications Interface to Synchronous Circuit having three stages is disclosed. The first stage captures the control and data signals from an asynchronous bus and converts them into signals which are synchronous to the internal clocks of the interface chip. The second stage of the interface is a synchronous state machine which utilizes the synchronized signals generated by the first stage to determine the current state of the asynchronous bus. The third stage of the interface uses the data generated by the synchronous state machine and the control and data signal capture logic to validate the data in a synchronous manner. This allows further processing of the data from the asynchronous bus without the use of any further asynchronous logic or timing.

摘要翻译： 公开了具有三个阶段的同步电路的异步通信接口。 第一级捕获来自异步总线的控制和数据信号，并将其转换成与接口芯片的内部时钟同步的信号。 接口的第二阶段是同步状态机，其利用由第一级产生的同步信号来确定异步总线的当前状态。 接口的第三级使用由同步状态机产生的数据和控制和数据信号捕获逻辑以同步方式验证数据。 这允许来自异步总线的数据的进一步处理，而不使用任何进一步的异步逻辑或时序。

公开(公告)号：US5459839A

公开(公告)日：1995-10-17

申请号：US293930

申请日：1994-08-22

申请人： Jeffery L. Swarts ,  Gary L. Rouse

发明人： Jeffery L. Swarts ,  Gary L. Rouse

IPC分类号： G06F5/06 ,  G06F13/12 ,  G06F9/32

CPC分类号： G06F13/126 ,  G06F5/065

摘要： A queue pointer manager contained in an integrated data controller is capable of controlling high speed data transfers between a high speed controlled data channel, a local processor bus and a dedicated local data bus. The overall design utilizes enhanced features of the Micro Channel architecture and data buffering to achieve maximum burst rates of 80 megabytes and to allow communications with 8, 16, 32 and 64 bit Micro Channel devices. Queued demands allow flexible programming of the Micro Channel master operations and reporting of completion statuses. The hardware control of command and status queuing functions increases the processing speed of control operations and reduces the need for software queuing. Extensive error checking/reporting, programming parameters, internal wrap self-test capability give the integrated data controller advanced functions as an input/output processor. The queue pointer manager also manages queue read and write pointers.

摘要翻译： 包含在集成数据控制器中的队列指针管理器能够控制高速受控数据信道，本地处理器总线和专用本地数据总线之间的高速数据传输。 整体设计利用Micro Channel架构和数据缓冲的增强功能，实现80 MB的最大突发速率，并允许与8,16,32和64位Micro Channel设备进行通信。 排队需求允许灵活编程Micro Channel主站操作并报告完成状态。 命令和状态排队功能的硬件控制提高了控制操作的处理速度，减少了对软件排队的需求。 广泛的错误检查/报告，编程参数，内部包装自检功能为集成数据控制器提供高级功能，作为输入/输出处理器。 队列指针管理器还管理队列读写指针。