公开(公告)号：US06720791B2

公开(公告)日：2004-04-13

申请号：US09940288

申请日：2001-08-27

Applicant: Jia-Shyong Cheng ,  Chia-Yu Wang ,  Shing-shiang Chang

Inventor： Jia-Shyong Cheng ,  Chia-Yu Wang ,  Shing-shiang Chang

IPC: G01R3100

CPC classification number: G09G3/006

Abstract: An LCD panel testing method. The method comprises forming jump lines in a predetermined region on the substrate between the signal lines via mask design when forming TFT LCD arrays, and thus forming a plurality of signal-line groups each with two signal lines coupled by the jump lines. Thereupon, an array tester sequentially tests two pixels corresponding to the signal lines in the signal groups. If one of the feedback signals from the signal groups does not meet a predetermined standard, it is determined that one or both pixels in the signal group are defective. The defective pixel or pixels are then identified using an electronic microscope to test two pixels at the same time. In this way, the number of probe pins and tests performed is halved. The probe pin size is also thus less restrictive due to larger probe pin intervals. Consequently, yield is greatly increased.

Abstract translation: 液晶面板测试方法。 该方法包括在形成TFT LCD阵列时通过掩模设计在信号线之间的衬底上的预定区域中形成跳线，从而形成多个信号线组，每条信号线分别由跳线连接两条信号线。 于是，阵列测试器依次测试对应于信号组中的信号线的两个像素。 如果来自信号组的反馈信号之一不满足预定标准，则确定信号组中的一个或两个像素有缺陷。 然后使用电子显微镜识别缺陷像素或像素，以同时测试两个像素。 以这种方式，探针数量和测试次数减半。 由于较大的探针引脚间隔，探针尺寸也因此受到限制。 因此，产量大大增加。

公开(公告)号：US06642071B2

公开(公告)日：2003-11-04

申请号：US10291065

申请日：2002-11-08

Applicant: Jia-Shyong Cheng

Inventor： Jia-Shyong Cheng

IPC: H01L2100

CPC classification number: G02F1/134363

Abstract: A TFT array substrate and a process for manufacturing the same are provided. A plurality of TFTs in array are formed on a substrate. A gate insulating layer and a protection layer are sequentially formed to cover a pixel region of the substrate. A plurality of openings each of which has an undercut profile are formed in the gate insulating layer and the protection layer. Then, a transparent conductive layer is formed over the substrate. One of the two parts separated is located in a bottom of the opening and the other is on the protection layer, such that two parts of the transparent conductive layer disconnect and no junction there between occurs. The part of the transparent conductive layer in the bottom of the opening is referred to as a transparent pixel electrode. The part of the transparent conductive layer on the protection layer is connected to a common metal line to form a transparent common electrode. The transparent pixel electrode disconnects to but overlaps the protection layer

Abstract translation: 提供TFT阵列基板及其制造方法。 阵列上的多个TFT形成在基板上。 依次形成栅极绝缘层和保护层以覆盖基板的像素区域。 在栅绝缘层和保护层中形成有多个开口，每个开口具有底切轮廓。 然后，在衬底上形成透明导电层。 分离的两个部件中的一个位于开口的底部，另一个位于保护层上，使得透明导电层的两个部分断开并且不发生连接。 将开口底部的透明导电层的一部分称为透明像素电极。 保护层上的透明导电层的一部分连接到公共金属线以形成透明公共电极。 透明像素电极断开，但与保护层重叠

公开(公告)号：US06057187A

公开(公告)日：2000-05-02

申请号：US164354

申请日：1998-10-01

Applicant: Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng

Inventor： Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng

IPC: H01L27/108 ,  H10L21/8242

CPC classification number: H01L27/10805 ,  H01L27/10808 ,  Y10S257/904 ,  Y10S257/906

Abstract: The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact. The DRAM structure of the present invention comprises: a substrate; an active region formed on the substrate, with a center region and a plurality of protrusion regions connecting to the two sides of the center region; a plurality of word-lines, disconnected from each other, each crossing the corresponding protrusion region; a plurality of channel regions, formed where the protrusion region overlaps with the word-lines; a plurality of source regions, formed at the outer areas of the channel regions; a sharing drain region, formed at the center region of the active region; a bit-line contact, formed on surface of the sharing drain region; a bit-line, crossing the center region and electrically connected to the sharing drain region via the bit-line contact; a plurality of capacitors, electrically connected to the source regions; and a plurality of metal lines, electrically connected to the corresponding word-lines.

Abstract translation: 本发明公开了具有共享相同位线接触的多个存储单元的DRAM结构。 本发明的DRAM结构包括：基板; 形成在所述基板上的有源区域，具有连接到所述中心区域的两侧的中心区域和多个突出区域; 多个字线彼此断开，每个字线与相应的突出区域交叉; 多个通道区域，形成在突起区域与字线重叠的位置上; 多个源区，形成在沟道区的外部区域; 形成在有源区的中心区域的共用漏极区; 形成在共享漏极区域的表面上的位线接触; 位线，穿过中心区域并且经由位线接触电连接到共享漏极区域; 多个电容器，电连接到源极区域; 和多个金属线，电连接到相应的字线。