公开(公告)号：US20230170331A1

公开(公告)日：2023-06-01

申请号：US18103315

申请日：2023-01-30

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L25/065 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/76897 ,  H01L2225/06548 ,  H01L2225/1058 ,  H01L2924/10253

Abstract: Systems and methods for multi-height interconnect structures for a semiconductor device are provided herein. The multi-height interconnect structure generally includes a primary level semiconductor die having a primary conductive pillar and a secondary conductive pillar, where the primary conductive pillar has a greater height than the secondary conductive pillar. The semiconductor device may further include a substrate electrically coupled to the primary level semiconductor die through the primary conductive pillar and a secondary level semiconductor die electrically coupled to the primary level semiconductor die through the secondary conductive pillar. The multi-height pillars may be formed using a single photoresist mask or multiple photoresist masks. In some configurations, the primary and secondary conductive pillars may be arranged on only the front-side of the dies and/or substrate.

公开(公告)号：US20230064032A1

公开(公告)日：2023-03-02

申请号：US17856197

申请日：2022-07-01

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00

Abstract: Exothermic reactive bonding for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die includes a dielectric layer having a conductive pad, where at least a portion of a surface of the dielectric layer includes a first epoxy compound. When another semiconductor die including a second epoxy compound (and another conductive pad) is brought in contact with the semiconductor die such that the first and second epoxy compounds can exothermically react, the thermal energy emanating from the exothermic reaction can facilitate bonding between the conductive pads to form interconnects between the two semiconductor dies. In some cases, the thermal energy is sufficient to form the interconnects. In other cases, the thermal energy assists the post bond annealing process to form the interconnects such that the annealing can be carried out at a lower temperature.

公开(公告)号：US20230050652A1

公开(公告)日：2023-02-16

申请号：US17673309

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Byung Hoon Moon ,  Kyle K. Kirby

IPC: H01L23/00

Abstract: Elastic bonding layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a first semiconductor die includes an elastic bonding layer at a surface, to which a second semiconductor die can be directly bonded to form a bonding interface between the first and second semiconductor dies. At the bonding interface, a first conductive pad of the first semiconductor die can be conjoined to a second conductive pad of the second semiconductor die to form an interconnect during the direct bonding process. In some cases, there may be irregularities at the bonding interface, which may interfere with the bonding process. The elastic bonding layer may include a polymer (or organic) material configured to accommodate stress generated by the irregularities. In some embodiments, a thickness of the elastic bonding layer is predetermined based on a width of the first (or second) conductive pad.

公开(公告)号：US11569203B2

公开(公告)日：2023-01-31

申请号：US16781707

申请日：2020-02-04

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L21/768 ,  H01L25/065

Abstract: Systems and methods for multi-height interconnect structures for a semiconductor device are provided herein. The multi-height interconnect structure generally includes a primary level semiconductor die having a primary conductive pillar and a secondary conductive pillar, where the primary conductive pillar has a greater height than the secondary conductive pillar. The semiconductor device may further include a substrate electrically coupled to the primary level semiconductor die through the primary conductive pillar and a secondary level semiconductor die electrically coupled to the primary level semiconductor die through the secondary conductive pillar. The multi-height pillars may be formed using a single photoresist mask or multiple photoresist masks. In some configurations, the primary and secondary conductive pillars may be arranged on only the front-side of the dies and/or substrate.

公开(公告)号：US20220157783A1

公开(公告)日：2022-05-19

申请号：US17589208

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other.

公开(公告)号：US20210242154A1

公开(公告)日：2021-08-05

申请号：US16781603

申请日：2020-02-04

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00

Abstract: An interconnect structure for a semiconductor device is provided herein. The interconnect structure generally includes a conductive pillar electrically coupled to a conductive contact positioned on a semiconductor die and a trace receiver on a distal end of the pillar. The trace receiver has a body electrically coupled to the distal end, and may include a first leg projecting from a first side of the body away from the distal end and a second leg projecting from a second side of the body away from the distal end, such that the body, the first leg, and the second leg together form a cavity. During assembly of the semiconductor device, the cavity is configured to at least partially surround a portion of a semiconductor trace positioned in an insulated substrate. To form the electrical connection, a solder material may be disposed between the trace receiver and the trace.

公开(公告)号：US20210183662A1

公开(公告)日：2021-06-17

申请号：US17189006

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Akshay N. Singh ,  Kyle K. Kirby

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

公开(公告)号：US11018056B1

公开(公告)日：2021-05-25

申请号：US16671577

申请日：2019-11-01

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Owen R. Fay

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L21/463 ,  H01L21/60

Abstract: A method of coupling a first semiconductor device to a second semiconductor device can include encapsulating solder balls on a first surface of a first substrate of the first semiconductor device with an encapsulant material. In some embodiments, the method includes removing a portion of the encapsulant material and a portion the solder balls to form a mating surface. The method can include reflowing the solder balls. In some embodiments, the method includes inserting exposed conductive pillars of the second semiconductor device into the reflowed solder balls.

公开(公告)号：US20210134725A1

公开(公告)日：2021-05-06

申请号：US16671558

申请日：2019-11-01

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.

公开(公告)号：US20210104451A1

公开(公告)日：2021-04-08

申请号：US17126455

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/48 ,  H01L49/02 ,  H01L23/538 ,  H01L25/065 ,  H01L23/522

Abstract: A semiconductor device includes a substrate, a plurality of circuit elements on a front side of the substrate, and a first substantially spiral-shaped conductor on a back side of the substrate is provided. The device further includes a first through-substrate via (TSV) electrically connecting a first end of the substantially spiral-shaped conductor to a first one of the plurality of circuit elements, and a second TSV electrically connecting a second end of the substantially spiral-shaped conductor to a second one of the plurality of circuit elements. The device may be a package further including a second die having a front side on which is disposed a second substantially spiral-shaped conductor. The front side of the second die is disposed facing the back side of the substrate, such that the first and second substantially spiral-shaped conductors are configured to wirelessly communicate.