公开(公告)号：US20250040027A1

公开(公告)日：2025-01-30

申请号：US18781616

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Byung Hoon Moon ,  Seng Kim Ye

IPC: H05K1/02 ,  H01L23/00 ,  H05K1/18

Abstract: A substrate is provided that includes a current limiter between Voltage Source (Vss) units on a Vss plane. The Vss plane includes a first Vss unit configured to provide a Vss signal to a first semiconductor device and a second Vss unit configured to provide a Vss signal to a second semiconductor device. The first and second Vss units include a first and second capacitor, respectively. The first and second capacitors are coupled through the current limiter, which can decrease the damage caused by electrostatic discharge events.

公开(公告)号：US20240071987A1

公开(公告)日：2024-02-29

申请号：US17898356

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Bang-Ning Hsu ,  Kyle K. Kirby ,  Byung Hoon Moon

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L24/05 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/80222 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor die is provided, comprising a semiconductor substrate, a dielectric layer over the semiconductor substrate, a bond pad in the dielectric layer, the bond pad including an exposed top surface that is recessed with respect to a surface of the dielectric layer opposite to the semiconductor substrate, and a region including a plurality of embedded nanoparticles in the dielectric layer, wherein the region is located proximate to the bond pad to supply thermal energy to the bond pad in response to exposing the plurality of embedded nanoparticles to an externally-applied field.

公开(公告)号：US20250140574A1

公开(公告)日：2025-05-01

申请号：US19011490

申请日：2025-01-06

Applicant: Micron Technology, Inc.

Inventor： Byung Hoon Moon

IPC: H01L21/56 ,  B29C33/42 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: Mold chases for molding semiconductor devices and/or components of semiconductor devices, the resulting semiconductor devices and/or their components, and related systems and methods are disclosed herein. In some embodiments, the mold chase includes a first clamp and a second clamp having a substrate engaging surface oriented towards the first clamp. The substrate engaging surface can have a hybrid surface texture that includes a first region and a second region at adjacent the first region (on a lateral side of the first region). The first region can include a first surface texture that is relatively smooth. The second region can include a second surface texture that is relatively rough compared to the first surface texture. The first surface texture can prevent mold bleed during a molding process. The second surface texture can reduce electrostatic discharge events during an ejection from the mold chase.

公开(公告)号：US12191164B2

公开(公告)日：2025-01-07

申请号：US17675949

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Byung Hoon Moon

IPC: H01L21/56 ,  B29C33/42 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: Mold chases for molding semiconductor devices and/or components of semiconductor devices, the resulting semiconductor devices and/or their components, and related systems and methods are disclosed herein. In some embodiments, the mold chase includes a first clamp and a second clamp having a substrate engaging surface oriented towards the first clamp. The substrate engaging surface can have a hybrid surface texture that includes a first region and a second region at adjacent the first region (on a lateral side of the first region). The first region can include a first surface texture that is relatively smooth. The second region can include a second surface texture that is relatively rough compared to the first surface texture. The first surface texture can prevent mold bleed during a molding process. The second surface texture can reduce electrostatic discharge events during an ejection from the mold chase.

公开(公告)号：US20240071986A1

公开(公告)日：2024-02-29

申请号：US17898330

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Byung Hoon Moon ,  Kyle K. Kirby

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/80234 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor die is provided, comprising a semiconductor substrate; a dielectric layer over the semiconductor substrate; a bond pad in the dielectric layer, the bond pad including an exposed top surface that is recessed with respect to a surface of the dielectric layer opposite to the semiconductor substrate; and a region of piezoelectric material in the dielectric layer, wherein the region is located proximate to the bond pad to supply thermal energy to the bond pad in response to exposing the piezoelectric material to an externally-applied field.

公开(公告)号：US20230268198A1

公开(公告)日：2023-08-24

申请号：US17675949

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Byung Hoon Moon

IPC: H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  B29C33/42

CPC classification number: H01L21/565 ,  H01L23/3121 ,  H01L25/0657 ,  H01L23/49894 ,  B29C33/42 ,  H01L2225/06562 ,  H01L2225/06506 ,  H01L2225/0651

Abstract: Mold chases for molding semiconductor devices and/or components of semiconductor devices, the resulting semiconductor devices and/or their components, and related systems and methods are disclosed herein. In some embodiments, the mold chase includes a first clamp and a second clamp having a substrate engaging surface oriented towards the first clamp. The substrate engaging surface can have a hybrid surface texture that includes a first region and a second region at adjacent the first region (on a lateral side of the first region). The first region can include a first surface texture that is relatively smooth. The second region can include a second surface texture that is relatively rough compared to the first surface texture. The first surface texture can prevent mold bleed during a molding process. The second surface texture can reduce electrostatic discharge events during an ejection from the mold chase.

公开(公告)号：US20230050652A1

公开(公告)日：2023-02-16

申请号：US17673309

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Byung Hoon Moon ,  Kyle K. Kirby

IPC: H01L23/00

Abstract: Elastic bonding layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a first semiconductor die includes an elastic bonding layer at a surface, to which a second semiconductor die can be directly bonded to form a bonding interface between the first and second semiconductor dies. At the bonding interface, a first conductive pad of the first semiconductor die can be conjoined to a second conductive pad of the second semiconductor die to form an interconnect during the direct bonding process. In some cases, there may be irregularities at the bonding interface, which may interfere with the bonding process. The elastic bonding layer may include a polymer (or organic) material configured to accommodate stress generated by the irregularities. In some embodiments, a thickness of the elastic bonding layer is predetermined based on a width of the first (or second) conductive pad.