公开(公告)号：US20200035287A1

公开(公告)日：2020-01-30

申请号：US16536141

申请日：2019-08-08

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Corrado Villa

IPC: G11C11/22 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.

公开(公告)号：US09070425B2

公开(公告)日：2015-06-30

申请号：US14068940

申请日：2013-10-31

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls ,  Howard Kirsch ,  Tae H. Kim

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C7/12

Abstract: Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. The second transistor can operate to couple the second data line to a second node during the first stage. The circuit can operate to apply a first signal to a gate of the first transistor during the operation and to apply a second signal to a gate of the second transistor during the operation. The sense amplifier can operate to perform a sense function on the first and second data lines during a second stage of the operation. Additional apparatus and methods are described.

Abstract translation: 一些实施例包括具有第一数据线，第二数据线，第一晶体管，读出放大器和电路的装置和方法。 在从与第一数据线相关联的存储器单元获得信息的操作的第一阶段期间，第一晶体管可以操作以将第一数据线耦合到第一节点。 第二晶体管可以在第一阶段期间将第二数据线耦合到第二节点。 电路可操作以在操作期间将第一信号施加到第一晶体管的栅极，并且在操作期间将第二信号施加到第二晶体管的栅极。 感测放大器可以在操作的第二阶段期间操作以在第一和第二数据线上执行感测功能。 描述附加的装置和方法。