公开(公告)号：US11500665B2

公开(公告)日：2022-11-15

申请号：US16520304

申请日：2019-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/455 ,  G06F12/1009 ,  G06F9/4401 ,  G06F9/48 ,  G06F13/10

Abstract: Systems, apparatuses, and methods related to a hypervisor status register in a computer processor are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store a value in the hypervisor status register during a power up process of the computer system. The value stored in the hypervisor status register that identifies whether or not an operating hypervisor is present in the computer system. The computer processor can configure its operations (e.g., address translation) based on the value stored in the hypervisor status register.

公开(公告)号：US20220261325A1

公开(公告)日：2022-08-18

申请号：US17738986

申请日：2022-05-06

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F11/26 ,  G06F9/30 ,  G06F11/22

Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.

公开(公告)号：US20220222078A1

公开(公告)日：2022-07-14

申请号：US17707278

申请日：2022-03-29

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30

Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.

公开(公告)号：US20220197648A1

公开(公告)日：2022-06-23

申请号：US17693240

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/30 ,  G06F9/34

Abstract: A computer system having an address system of a first predetermined width in which each address of the first predetermined width in the address system includes a first portion identifying an object and a second portion identifying an offset relative to the object, where a static identifier for the first portion is predetermined to identify an address space having a second predetermined width that is smaller than the first predetermined width, or a space of kernel objects.

公开(公告)号：US11340904B2

公开(公告)日：2022-05-24

申请号：US16417500

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/34 ,  G06F9/35 ,  G06F9/30 ,  G06F15/80 ,  G06F9/345 ,  G06F9/355

Abstract: Disclosed herein are vector index registers in vector processors that each store multiple addresses for accessing multiple positions in vectors. It is known to use scalar index registers in vector processors to access multiple positions of vectors by changing the scalar index registers in vector operations. By using a vector indexing register for indexing positions of one or more operand vectors, the scalar index register can be replaced and at least the continual changing of the scalar index register can be avoided.

公开(公告)号：US11307861B2

公开(公告)日：2022-04-19

申请号：US16942591

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30

Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.

公开(公告)号：US20220083341A1

公开(公告)日：2022-03-17

申请号：US17534780

申请日：2021-11-24

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F12/0891 ,  G06F12/0811 ,  G06F13/20 ,  G06F12/0831

Abstract: A cache system having cache sets, and the cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system also has a control register and a mapping circuit coupled to the control register to map respective physical outputs of the cache sets to a first logical cache and a second logical cache according to a state of the control register. The first logical cache can be a normal or main cache for non-speculative executions by a processor and the second logical cache can be a shadow cache for speculative executions by the processor.

公开(公告)号：US11200166B2

公开(公告)日：2021-12-14

申请号：US16528471

申请日：2019-07-31

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/0806 ,  G06F9/38 ,  G06F13/36

Abstract: A cache system, having: a first cache; a second cache; a configurable data bit; and a logic circuit coupled to a processor to control the caches based on the configurable bit. When the configurable bit is in a first state, the logic circuit is configured to: implement commands for accessing a memory system via the first cache, when an execution type is a first type; and implement commands for accessing the memory system via the second cache, when the execution type is a second type. When the configurable data bit is in a second state, the logic circuit is configured to: implement commands for accessing the memory system via the second cache, when the execution type is the first type; and implement commands for accessing the memory system via the first cache, when the execution type is the second type.

公开(公告)号：US20210349724A9

公开(公告)日：2021-11-11

申请号：US16942591

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30

Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.

公开(公告)号：US11100254B2

公开(公告)日：2021-08-24

申请号：US16210605

申请日：2018-12-05

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F21/14 ,  G06F21/74 ,  G06F21/72 ,  G06F9/30 ,  G06F12/1036 ,  G06F21/60

Abstract: Methods, systems, and apparatuses related to adjustable security levels in processors are described. A processor may have functional units and a register configured to control security operations of the functional units. The register configures the functional units to operate in a first mode of security operations when the register contains a first setting; and the register configures the functional units to operate in a second mode of security operations when the register contains a second setting (e.g., to skip/bypassing a set of security operation circuit for enhanced execution speed).