公开(公告)号：US11251149B2

公开(公告)日：2022-02-15

申请号：US17485504

申请日：2021-09-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L21/46 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/544 ,  H01L25/00

Abstract: A semiconductor device, the device including: a first level overlaid by a first memory level, where the first memory level includes a first thinned single crystal substrate; a second memory level, the second memory level disposed on top of the first memory level, where the second memory level includes a second thinned single crystal substrate; and a memory control level disposed on top of the second memory level, where the memory control level is bonded to the second memory level, and where the bonded includes oxide to oxide and conductor to conductor bonding.

公开(公告)号：US11233069B2

公开(公告)日：2022-01-25

申请号：US17396711

申请日：2021-08-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/11582 ,  H01L29/47 ,  H01L29/78 ,  H01L29/167 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/02 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11514 ,  H01L27/11551 ,  H01L27/11519

Abstract: A 3D device, the device including: a first level including logic circuits; and a second level including a plurality of memory cells, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the logic circuits include a programmable logic circuit.

公开(公告)号：US20220005821A1

公开(公告)日：2022-01-06

申请号：US17461075

申请日：2021-08-30

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H01L27/11556 ,  H01L27/11582

Abstract: A 3D memory device, the device including: a first vertical pillar, the first vertical pillar includes a transistor source; a second vertical pillar, the second vertical pillar includes the transistor drain, where the first vertical pillar and the second vertical pillar each functions as a source or functions as a drain for a plurality of overlaying horizontally-oriented memory transistors, where at least of one of the plurality of overlaying horizontally-oriented memory transistors is disposed between the first vertical pillar and the second vertical pillar, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following a same lithography step, and where the first vertical pillar includes metal.

公开(公告)号：US20210375921A1

公开(公告)日：2021-12-02

申请号：US17396711

申请日：2021-08-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/11582 ,  H01L29/47 ,  H01L29/78 ,  H01L29/167 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/02 ,  H01L27/11578 ,  H01L29/792

Abstract: A 3D device, the device including: a first level including logic circuits; and a second level including a plurality of memory cells, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the logic circuits include a programmable logic circuit.

公开(公告)号：US11158652B1

公开(公告)日：2021-10-26

申请号：US17346295

申请日：2021-06-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C16/04 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  G11C7/18 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel is isolated from another channel disposed directly above the channel.

公开(公告)号：US11121121B2

公开(公告)日：2021-09-14

申请号：US16558304

申请日：2019-09-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/46 ,  H01L25/00

Abstract: A 3D semiconductor device, the device including: a first level; a second level; and a third level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits includes a first logic circuit and a second logic circuit, where the second level is disposed directly above the first level and includes a first plurality of arrays of memory cells, where the third level is disposed directly above the second level and includes a plurality of on-chip RF circuits, and where a portion of interconnections between the first logic circuit and the second logic circuit includes the plurality of on-chip RF circuits.

公开(公告)号：US11114427B2

公开(公告)日：2021-09-07

申请号：US16786060

申请日：2020-02-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than four microns, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.

公开(公告)号：US11107803B2

公开(公告)日：2021-08-31

申请号：US17214883

申请日：2021-03-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L21/30 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: A method to construct a 3D system, the method including: providing a base wafer; and then transferring a memory control on top; and then thinning the memory control, transferring a first memory wafer on top; and then thinning the first memory wafer; and then transferring a second memory wafer on top; and then thinning the second memory wafer. A 3D device, the device including: a first stratum including first bit-cell memory arrays; a second stratum including second bit-cell memory arrays; and a third stratum, where the second stratum overlays the first stratum, where the first stratum overlays the third stratum, where the third stratum includes a plurality of word-line decoders to control the first bit-cell memory arrays and the second bit-cell memory arrays.

公开(公告)号：US11018156B2

公开(公告)日：2021-05-25

申请号：US17099706

申请日：2020-11-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C16/04 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  G11C7/18 ,  H01L27/11565

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source and a drain; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where each of the plurality of bit-line pillars includes metal atoms such that the plurality of bit-line pillars have at least partial metallic properties; and a thermal path from the bit-line pillars to an external surface of the device to remove heat. Various 3D processing flows and methods are also disclosed.

公开(公告)号：US10418369B2

公开(公告)日：2019-09-17

申请号：US15990611

申请日：2018-05-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/115 ,  H01L27/112 ,  H01L27/11556 ,  H01L23/48 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11582 ,  G11C5/02 ,  G11C13/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C17/16 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/24

Abstract: A multilevel semiconductor device including: a first level including a first array of first memory cells and first control line; a second level including a second array of second memory cells and second control line; a third level including a third array of third memory cells and third control line, where the second level overlays the first, and where the third level overlays the second; a first, second and third access pillar; memory control circuits designed to individually control cells of the first, second and third memory cells, where the device includes an array of units, where each of the units includes a plurality of the first, second and third memory cells, and a portion of the memory control circuits, where the array of units include at least eight rows and eight columns of units, and where the memory control is designed to control independently each of the units.