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71.发明授权Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module 有权缓冲存储器模块在与传统存储器模块相同的物理空间中支持存储器件数据宽度的两倍公开(公告)号：US07899983B2
公开(公告)日：2011-03-01
申请号：US11848335
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F13/00
CPC分类号： H05K1/181 , G11C5/04 , H05K2201/10159 , H05K2201/10515 , Y02P70/611
摘要： A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated into a memory module, a first memory device data interface integrated that communicates with a first set of memory devices and a second memory device data interface integrated that communicates with a second set of memory devices. In the memory system, the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module and the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate. In the memory system, data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.
摘要翻译： 提供了一种存储器系统，其增强了通过存储器模块可用的存储器带宽。 存储器系统包括集成到存储器模块中的存储器集线器装置，集成了与第一组存储器件通信的第一存储器件数据接口和与第二组存储器件通信的集成的第二存储器件数据接口。 在存储器系统中，第一组存储器件在第一平面中间隔开并且耦合到存储器模块的衬底，并且第二组存储器件在第一平面上方的第二平面上间隔开并耦合到衬底。 在存储器系统中，第一组存储器件的数据总线与第二组存储器件的数据总线分开耦合到衬底。
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72.发明授权公开(公告)号：US07865674B2
公开(公告)日：2011-01-04
申请号：US11848309
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/4059 , G06F13/1684
摘要： A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.
摘要翻译： 提供了一种存储器系统，其增强了通过存储器模块可用的存储器带宽。 存储器系统包括集成在存储器模块中的存储器集线器设备。 存储器系统包括集成在存储器集线器设备中的第一存储器设备数据接口，其与集成在存储器模块中的第一组存储器设备进行通信。 存储器系统还包括集成在存储器集线器设备中的第二存储器设备数据接口，其与集成在存储器模块中的第二组存储器设备进行通信。 在存储器系统中，第一组存储器件与第二组存储器件分开。 在存储器系统中，第一和第二组存储器设备经由独立的第一和第二存储器件数据接口由存储器集线器设备进行通信。
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公开(公告)号：US07818497B2
公开(公告)日：2010-10-19
申请号：US11848322
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00 , G11C11/4093
CPC分类号： G06F13/1668
摘要： A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and a memory module coupled to the memory controller. In the memory system, the memory controller is coupled to the memory module via at least two independent memory channels. In the memory system, the at least two independent memory channels are coupled to one or more memory hub devices of the memory module.
摘要翻译： 提供了一种存储器系统，其增强了通过存储器模块可用的存储器带宽。 存储器系统包括存储器控制器和耦合到存储器控制器的存储器模块。 在存储器系统中，存储器控制器经由至少两个独立存储器通道耦合到存储器模块。 在存储器系统中，至少两个独立存储器通道耦合到存储器模块的一个或多个存储器集线器装置。
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74.发明授权276-pin buffered memory module with enhanced memory system interconnect and features 有权276针缓冲内存模块，具有增强的内存系统互连和功能公开(公告)号：US07717752B2
公开(公告)日：2010-05-18
申请号：US12166227
申请日：2008-07-01
IPC分类号： H01R24/00
CPC分类号： G11C5/04 , H01R12/721
摘要： A memory subsystem system including a rectangular printed circuit card having a first side and a second side, a length of between 149.5 and 153.5 millimeters, and first and second ends having a width smaller than the length. The memory system also includes a first plurality of pins on the first side extending along a first edge of the card that extends the length of the card, and a second plurality of pins on the second side extending on the first edge of the card. The memory system further includes a positioning key having it center positioned on the first edge of the card and located between 84.5 and 88.5 millimeters from the first end of the card and located between 62.5 and 66.5 millimeters from the second end of the card.
摘要翻译： 一种存储器子系统，包括具有第一侧和第二侧的矩形印刷电路卡，长度在149.5和153.5毫米之间，第一和第二端具有小于该长度的宽度。 存储器系统还包括在第一侧上沿着延长卡的长度的卡的第一边缘延伸的第一多个销，以及在卡的第一边缘上延伸的第二侧上的第二多个销。 存储系统还包括定位键，其中心位于卡的第一边缘上，并位于距离卡的第一端84.5至88.5毫米之间，并位于距卡的第二端62.5至66.5毫米之间。
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公开(公告)号：US20100005366A1
公开(公告)日：2010-01-07
申请号：US12166235
申请日：2008-07-01
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0781 , G06F11/1004 , G11C5/04 , G11C29/70 , G11C2029/0409 , G11C2029/0411
摘要： A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device. Responding to the error includes recording a severity level of the failure in the FIR and taking an action at the hub device that is responsive to the severity level of the failure. The action includes one or more of fast clock stop, setting the bi-directional fault indicator, setting cyclical redundancy code (CRC) bits and transmitting them to the memory controller, re-try, sparing out a bit lane and sparing out a clock lane.
摘要翻译： 一种用于提供具有增强的可靠性的级联互连存储器系统的集线器设备，存储器系统和方法。 集线器设备包括与高速总线的接口，用于与存储器控制器进行通信。 存储器控制器和集线器设备包括在级联互连存储器系统中，并且高速总线包括位通道和一个或多个时钟通道。 集线器设备还包括与存储器控制器通信并可由服务接口读取的双向故障信号线。 集线器设备还包括用于存储关于在集线器设备处检测到的故障的信息的故障隔离寄存器（FIR），该信息包括检测到的故障的严重性级别。 此外，集线器设备包括用于响应在集线器设备处检测到的故障的错误恢复逻辑。 响应该错误包括在FIR中记录故障的严重性级别，并在响应于故障严重性级别的集线器设备上执行操作。 该动作包括一个或多个快速时钟停止，设置双向故障指示器，设置循环冗余码（CRC）位并将其发送到存储器控制器，重新尝试，省略一个位线并省出一个时钟通道 。
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76.发明申请276-PIN BUFFERED MEMORY MODULE WITH ENHANCED MEMORY SYSTEM INTERCONNECT AND FEATURES 审中-公开具有增强的存储器系统的276引脚缓冲存储器模块互连和特性公开(公告)号：US20100005219A1
公开(公告)日：2010-01-07
申请号：US12166185
申请日：2008-07-01
CPC分类号： G11C5/04 , G06F11/1666 , G06F11/20 , G11C7/02 , G11C7/04 , G11C29/022
摘要： A memory module including a plurality of memory channel connectors for communicating with a memory controller via a plurality of high-speed channels. The memory module also includes a plurality of memory devices arranged in one or more ranks, and a plurality of independently operable hub devices. Each hub device includes an interface for receiving signals from and driving signals to the memory controller on one of the high-speed channels via one or more of the memory channel connectors. Each hub device also includes a plurality of independently operable ports to communicate with all or a subset of the ranks of memory devices.
摘要翻译： 一种存储模块，包括多个存储器通道连接器，用于经由多个高速通道与存储器控制器进行通信。 存储器模块还包括以一个或多个等级排列的多个存储器件，以及多个可独立操作的集线器器件。 每个集线器设备包括用于经由一个或多个存储器通道连接器从高速通道中的一个上接收信号并将信号驱动到存储器控制器的接口。 每个集线器设备还包括多个可独立操作的端口，以与存储器设备的所有等级的全部或一部分进行通信。
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77.发明授权System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel 失效用于将部分高速缓存行写入操作支持到存储器模块以减少存储器通道上的写入数据流量的系统公开(公告)号：US07584308B2
公开(公告)日：2009-09-01
申请号：US11848342
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F13/00
CPC分类号： G06F13/161
摘要： A memory system is provided that supports partial cache line write operations to a memory module to reduce write data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises burst logic integrated in the memory hub device. The burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of write data that is transmitted using the burst length field. The memory hub device transmits the amount of write data that is equal to or less than a conventional data burst amount.
摘要翻译： 提供了一种存储器系统，其支持对存储器模块的部分高速缓存行写入操作以减少存储器通道上的写入数据流量。 存储器系统包括集成在存储器模块中的存储器集线器设备和耦合到存储器集线器设备的一组存储器设备。 存储器集线器设备包括集成在存储器集线器设备中的突发逻辑。 突发逻辑确定要发送到存储器装置集合的写入数据量，并产生与写入数据量对应的突发长度字段。 存储器集线器还包括集成在存储器集线器设备中的存储器集线器控制器。 存储器集线器控制器控制使用突发长度字段发送的写入数据量。 存储器集线器设备发送等于或小于常规数据突发量的写入数据量。
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78.发明申请System to Enable a Memory Hub Device to Manage Thermal Conditions at a Memory Device Level Transparent to a Memory Controller 失效用于启用内存集线器设备以管理存储器设备级别的热条件的系统对内存控制器透明公开(公告)号：US20090190427A1
公开(公告)日：2009-07-30
申请号：US12018972
申请日：2008-01-24
IPC分类号： G11C7/04
摘要： A memory system is provided that manages thermal conditions at a memory device level transparent to a memory controller. The memory systems comprises a memory hub device integrated in a memory module, a set of memory devices coupled to the memory hub device, and a first set of thermal sensors integrated in the set of memory devices. A thermal management control unit integrated in the memory hub device monitors a temperature of the set of memory devices sensed by the first set of thermal sensors. The memory hub device reduces a memory access rate to the set of memory devices in response to a predetermined thermal threshold being exceeded thereby reducing power used by the set of memory devices which in turn decreases the temperature of the set of memory devices.
摘要翻译： 提供了一种存储系统，其管理对存储器控制器透明的存储器设备级的热条件。 存储器系统包括集成在存储器模块中的存储器集线器设备，耦合到存储器集线器设备的一组存储器设备和集成在该组存储器设备中的第一组热传感器。 集成在存储器集线器设备中的热管理控制单元监视由第一组热传感器感测的存储器组的温度。 存储器集线器设备响应于超过预定的热阈值而将存储器访问速率降低到存储器设备组，从而减少由该组存储器件使用的功率，这又降低了该组存储器件的温度。
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79.发明申请Buffered Memory Module Supporting Double the Memory Device Data Width in the Same Physical Space as a Conventional Memory Module 有权缓冲内存模块支持在与传统内存模块相同的物理空间中将内存设备数据宽度加倍公开(公告)号：US20090063785A1
公开(公告)日：2009-03-05
申请号：US11848335
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： H05K1/181 , G11C5/04 , H05K2201/10159 , H05K2201/10515 , Y02P70/611
摘要： A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated into a memory module, a first memory device data interface integrated that communicates with a first set of memory devices and a second memory device data interface integrated that communicates with a second set of memory devices. In the memory system, the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module and the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate. In the memory system, data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.
摘要翻译： 提供了一种存储器系统，其增强了通过存储器模块可用的存储器带宽。 存储器系统包括集成到存储器模块中的存储器集线器装置，集成了与第一组存储器件通信的第一存储器件数据接口和与第二组存储器件通信的集成的第二存储器件数据接口。 在存储器系统中，第一组存储器件在第一平面中间隔开并且耦合到存储器模块的衬底，并且第二组存储器件在第一平面上方的第二平面上间隔开并耦合到衬底。 在存储器系统中，第一组存储器件的数据总线与第二组存储器件的数据总线分开耦合到衬底。
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公开(公告)号：US20090063761A1
公开(公告)日：2009-03-05
申请号：US11848322
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/1668
摘要： A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and a memory module coupled to the memory controller. In the memory system, the memory controller is coupled to the memory module via at least two independent memory channels. In the memory system, the at least two independent memory channels are coupled to one or more memory hub devices of the memory module.
摘要翻译： 提供了一种存储器系统，其增强了通过存储器模块可用的存储器带宽。 存储器系统包括存储器控制器和耦合到存储器控制器的存储器模块。 在存储器系统中，存储器控制器经由至少两个独立存储器通道耦合到存储器模块。 在存储器系统中，至少两个独立存储器通道耦合到存储器模块的一个或多个存储器集线器装置。
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