System and method of generating dynamic word line from the content addressable memory (CAM) “hit/miss” signal which is scannable for testability
    71.
    发明授权
    System and method of generating dynamic word line from the content addressable memory (CAM) “hit/miss” signal which is scannable for testability 有权
    从内容可寻址存储器(CAM)生成动态字线的系统和方法“可靠性可扫描”的“命中/未命中”信号

    公开(公告)号:US06564344B1

    公开(公告)日:2003-05-13

    申请号:US09435866

    申请日:1999-11-08

    CPC classification number: G11C15/00 G11C29/12

    Abstract: Each match word line driver circuit associated with a content addressable memory (CAM) utilizes a scannable latch for testing. The scannable latches associated with a particular CAM are connected together, scan output of one to scan input of the next, forming a scanning latch chain. In test mode the scannable dynamic latch is used either for testing CAM match circuits or for driving word lines to test the RAM array. Testing CAM match circuits is accomplished by patterning the CAM array with known storage values. The match circuitry then compares an effective address to each storage value and the results are scanned out. Testing the RAM array is performed by driving each word line with a known scan value. Each word line responds the scan value and a sense amplifier outputs a RAM array value based on the word line.

    Abstract translation: 与内容可寻址存储器(CAM)相关联的每个匹配字线驱动器电路利用可扫描的锁存器进行测试。 与特定CAM相关联的可扫描闩锁连接在一起,扫描一个的扫描输出以扫描下一个的输入,形成扫描锁存链。 在测试模式下,可扫描动态锁存器用于测试CAM匹配电路或用于驱动字线以测试RAM阵列。 测试CAM匹配电路通过用已知存储值对CAM阵列进行图案化来实现。 匹配电路然后将有效地址与每个存储值进行比较,并将结果扫描出来。 通过用已知扫描值驱动每个字线来执行RAM阵列的测试。 每个字线响应扫描值,读出放大器基于字线输出RAM阵列值。

    Dynamic sense amplifier with embedded latch
    72.
    发明授权
    Dynamic sense amplifier with embedded latch 失效
    具有嵌入式锁存器的动态读出放大器

    公开(公告)号:US5963495A

    公开(公告)日:1999-10-05

    申请号:US024807

    申请日:1998-02-17

    Applicant: Manoj Kumar

    Inventor: Manoj Kumar

    CPC classification number: G11C7/065

    Abstract: A dynamic sense amplifier (10) cooperates with an embedded latch arrangement for converting signals read from a memory cell array to digital signals. The dynamic sense amplifier (10) is connected to a complementary pair of data output lines, each associated with a data output node, and to a complementary pair of data lines from a column decoder associated with the memory cell array. The dynamic sense amplifier (10) is also connected to a sense enable line for receiving a sense enable signal, while the latch incorporated in the dynamic sense amplifier (10) is connected to a latch enable line. The dynamic sense amplifier (10) operates to quickly develop an intermediate charge state at the data output nodes in response to a read charge state on the data lines and a sense enable signal applied at the sense enable line. After developing the intermediate charge state, the latch enable signal is applied to the latch enable line to take the intermediate charge state to a final charge state at the data output nodes. This final charge state at the data output nodes produces data signals on the data output lines. The latch also operates in response to the latch enable signal to hold the charge at the data output nodes, thereby holding the data at the data output lines.

    Abstract translation: 动态读出放大器(10)与嵌入式锁存装置协作,用于将从存储单元阵列读取的信号转换成数字信号。 动态感测放大器(10)连接到互补数据输出线对,每条数据输出线与数据输出节点相关联,并连接到与存储器单元阵列相关联的列解码器的互补数据线对。 动态感测放大器(10)还连接到感测使能线,用于接收感测使能信号,而并入动态读出放大器(10)中的锁存器连接到锁存使能线。 动态感测放大器(10)响应于数据线上的读取电荷状态和在感测使能线处施加的感测使能信号,在数据输出节点处快速地形成中间充电状态。 在开发中间充电状态之后,将锁存使能信号施加到锁存使能线,以将中间充电状态置于数据输出节点处的最终充电状态。 在数据输出节点处的最终充电状态在数据输出线上产生数据信号。 锁存器还响应于锁存使能信号而操作,以将数据输出节点上的电荷保持在数据输出线上。

    Two mode sense amplifier with latch
    73.
    发明授权
    Two mode sense amplifier with latch 失效
    两个模式读出放大器带锁存器

    公开(公告)号:US5526314A

    公开(公告)日:1996-06-11

    申请号:US352659

    申请日:1994-12-09

    Applicant: Manoj Kumar

    Inventor: Manoj Kumar

    CPC classification number: G11C7/062 G11C7/065

    Abstract: A sense amplifier apparatus for use in a memory array having a plurality of memory cells is provided. The sense amplifier apparatus includes a differential sense amplifier and a dynamic sense amplifier. The differential sense amplifier has a first set of switches for driving the voltages of the sense amplifier apparatus and are coupled to a complementary pair of outputs. Also provided are a second set of switches, which are coupled to a complementary pair of input lines so as to amplify the input signal on either of the pair of input lines to a first signal level at a first rate of amplification. The dynamic sense amplifier shares the first set of switches with the differential sense amplifier and further includes a third set of switches that are coupled to a complementary pair of input lines and the output lines and also a sense enable line. This allows the first signal level to be amplified to a second signal level at a second rate of amplification faster than the first rate of amplification.

    Abstract translation: 提供一种用于具有多个存储单元的存储器阵列中的读出放大器装置。 读出放大器装置包括差分读出放大器和动态读出放大器。 差分读出放大器具有第一组开关,用于驱动读出放大器装置的电压,并耦合到互补输出对。 还提供了第二组开关,其耦合到互补的一对输入线,以便将第一对输入线中的任一个上的输入信号以第一放大率放大到第一信号电平。 动态感测放大器与差分读出放大器共享第一组开关,并且还包括耦合到互补输入线对和输出线以及感测使能线的第三组开关。 这允许第一信号电平以比第一扩展速率快的第二放大速率被放大到第二信号电平。

    Reset generation circuit to reset self resetting CMOS circuits
    74.
    发明授权
    Reset generation circuit to reset self resetting CMOS circuits 失效
    复位发生电路以复位自复位CMOS电路

    公开(公告)号:US5467037A

    公开(公告)日:1995-11-14

    申请号:US342967

    申请日:1994-11-21

    CPC classification number: H03K3/356008

    Abstract: A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.

    Abstract translation: 自复位CMOS(SRCMOS)电路以可变的时钟周期工作。 在长或短时钟周期内避免电路振荡。 同时,该电路通过并入接地中断装置来消除重叠电流。 复位产生路径被优化以提供快速和窄的复位脉冲。 此外,电路节省电力。

    Method to automatically map business function level policies to IT management policies
    77.
    发明授权
    Method to automatically map business function level policies to IT management policies 有权
    自动将业务功能级别策略映射到IT管理策略的方法

    公开(公告)号:US08914844B2

    公开(公告)日:2014-12-16

    申请号:US13553342

    申请日:2012-07-19

    CPC classification number: G06F21/604 G06F2221/2101

    Abstract: A method, system, computer program product, and computer program storage device for transforming a high-level policy associated with a high layer to a low-level policy associated with a low layer. Mapping between high-level objects in a high layer and low-level objects in a low layer is derived by an automated discovery tool. The high-level policy is mapped to the low-level policy according to the mapping (e.g., by substituting the high-level objects with the low-level objects and by performing a syntax transformation). In one embodiment, a low-level policy is transformed to a high-level policy according to the mapping. As exemplary embodiments, policy transformations in traffic shaping and data retention are disclosed.

    Abstract translation: 一种用于将与高层相关联的高级策略变换为与低层相关联的低级策略的方法,系统,计算机程序产品和计算机程序存储设备。 高层的高层对象与低层对象之间的映射是通过自动发现工具得出的。 高级策略根据映射映射到低级策略(例如,通过用低级对象替换高级对象,并通过执行语法转换)。 在一个实施例中,根据映射将低级策略转换为高级策略。 作为示例性实施例,公开了流量整形和数据保持中的策略转换。

    METHOD AND SYSTEM FOR MANAGING CREDIT DISPUTES ASSOCIATED WITH ACCOUNT PAYABLES OF AN ORGANIZATION
    78.
    发明申请
    METHOD AND SYSTEM FOR MANAGING CREDIT DISPUTES ASSOCIATED WITH ACCOUNT PAYABLES OF AN ORGANIZATION 审中-公开
    管理与组织的帐户付款相关的信用争议的方法和系统

    公开(公告)号:US20140114820A1

    公开(公告)日:2014-04-24

    申请号:US14058826

    申请日:2013-10-21

    Applicant: Manoj Kumar

    Inventor: Manoj Kumar

    CPC classification number: G06Q40/10

    Abstract: The various embodiments herein provide a method and system for managing credit disputes associated with account payables of an organization. The method comprises of fetching a current version of a variance data from a database, determining whether the variance data matches with a pre-recorded data, creating a claim for a discrepancy in the variance data if the variance data does not match with the pre-recorded data and generating one or more notifications based on the discrepancy. The variance data comprises at least one of purchase order information, invoice information; items received information and payment information. Once the claim has been created the credit that comes back is match to wring every single penny.

    Abstract translation: 本文的各种实施例提供了用于管理与组织的应付账款相关联的信用纠纷的方法和系统。 该方法包括从数据库中获取当前版本的方差数据,确定方差数据是否与预先记录的数据匹配,如果方差数据与预先记录的数据不匹配,则创建方差数据中的差异的权利要求, 记录数据并基于差异生成一个或多个通知。 差异数据包括采购订单信息,发票信息中的至少一个; 项目收到信息和付款信息。 一旦创建了索赔,返回的信用证就会扣上每一分钱。

    Method to automatically map business function level policies to IT management policies
    79.
    发明授权
    Method to automatically map business function level policies to IT management policies 失效
    自动将业务功能级别策略映射到IT管理策略的方法

    公开(公告)号:US08595792B2

    公开(公告)日:2013-11-26

    申请号:US13553332

    申请日:2012-07-19

    CPC classification number: G06F21/604 G06F2221/2101

    Abstract: A method, system, computer program product, and computer program storage device for transforming a high-level policy associated with a high layer to a low-level policy associated with a low layer. Mapping between high-level objects in a high layer and low-level objects in a low layer is derived by an automated discovery tool. The high-level policy is mapped to the low-level policy according to the mapping (e.g., by substituting the high-level objects with the low-level objects and by performing a syntax transformation). In one embodiment, a low-level policy is transformed to a high-level policy according to the mapping. As exemplary embodiments, policy transformations in traffic shaping and data retention are disclosed.

    Abstract translation: 一种用于将与高层相关联的高级策略变换为与低层相关联的低级策略的方法,系统,计算机程序产品和计算机程序存储设备。 高层的高层对象与低层对象之间的映射是通过自动发现工具得出的。 高级策略根据映射映射到低级策略(例如,通过用低级对象替换高级对象,并通过执行语法转换)。 在一个实施例中,根据映射将低级策略转换为高级策略。 作为示例性实施例,公开了流量整形和数据保持中的策略转换。

    Analytics integration server within a comprehensive framework for composing and executing analytics applications in business level languages
    80.
    发明授权
    Analytics integration server within a comprehensive framework for composing and executing analytics applications in business level languages 有权
    全面的框架中的分析集成服务器,用于以业务级语言编写和执行分析应用程序

    公开(公告)号:US08401993B2

    公开(公告)日:2013-03-19

    申请号:US12559388

    申请日:2009-09-14

    CPC classification number: G06Q10/10

    Abstract: Systems, methods and articles of manufacture are disclosed for building and executing analytics solutions. Such a solution may provide a comprehensive analytics solution (e.g., a risk assessment, fraud detection solution, dynamic operational risk evaluations, regulatory compliance assessments, etc.). The analytics solution may perform an analytics task using operational data distributed across a variety of independently created and governed data repositories in different departments of an organization. A framework is disclosed which allows a user (e.g., a risk analyst) to compose analytical tools that can access data from a variety of sources (both internal and external to an enterprise) and perform a variety of analytic functions.

    Abstract translation: 披露了构建和执行分析解决方案的系统,方法和制造。 这样的解决方案可以提供全面的分析解决方案(例如,风险评估,欺诈检测解决方案,动态操作风险评估,监管合规性评估等)。 分析解决方案可以使用分布在组织不同部门的各种独立创建和管理的数据存储库中的操作数据执行分析任务。 公开了允许用户(例如,风险分析员)组成可以从各种来源(企业内部和外部)访问数据并执行各种分析功能的分析工具的框架。

Patent Agency Ranking