公开(公告)号：US5467037A

公开(公告)日：1995-11-14

申请号：US342967

申请日：1994-11-21

申请人： Manoj Kumar ,  George M. Lattimore ,  Joseph M. Poplawski, Jr.

发明人： Manoj Kumar ,  George M. Lattimore ,  Joseph M. Poplawski, Jr.

IPC分类号： H03K3/356 ,  H03L7/00

CPC分类号： H03K3/356008

摘要： A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.

摘要翻译： 自复位CMOS（SRCMOS）电路以可变的时钟周期工作。 在长或短时钟周期内避免电路振荡。 同时，该电路通过并入接地中断装置来消除重叠电流。 复位产生路径被优化以提供快速和窄的复位脉冲。 此外，电路节省电力。

公开(公告)号：US5615168A

公开(公告)日：1997-03-25

申请号：US538085

申请日：1995-10-02

申请人： George M. Lattimore ,  Michael K. Ciraula ,  Manoj Kumar ,  Joseph M. Poplawski, Jr. ,  Dieter F. Wendel ,  Friedrich Wernicke

发明人： George M. Lattimore ,  Michael K. Ciraula ,  Manoj Kumar ,  Joseph M. Poplawski, Jr. ,  Dieter F. Wendel ,  Friedrich Wernicke

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1072

摘要： A method and apparatus for providing single clock cycle pipelined access of a memory system, which combines synchronization and self resetting techniques, includes an array of memory cells that are arranged into columns and rows and intercoupled by bit lines and word lines. The memory system also includes an address decoder and a sense enable circuit. The address decoder, upon receiving an address, interprets the address to enable a particular word line, or word lines, and to disable precharging of a bit line, or bit lines. With the word line active, the sense enable circuit generates a sense enable signal when the clock signal has encountered a transitional edge, or is in an active state. When the sense enable signal is active, the sense amplifier reads the data from the addressed memory cell via the bit lines to produce output data.

摘要翻译： 用于提供组合同步和自复位技术的存储器系统的单时钟周期流水线访问的方法和装置包括排列成列和行并由位线和字线相互配合的存储器单元阵列。 存储器系统还包括地址解码器和感测使能电路。 地址解码器在接收到地址后，解释地址以启用特定字线或字线，并禁止位线或位线的预充电。 当字线有效时，当时钟信号遇到过渡沿或处于活动状态时，感测使能电路产生检测使能信号。 当感测使能信号有效时，读出放大器通过位线从寻址的存储单元读取数据，以产生输出数据。

公开(公告)号：US5544112A

公开(公告)日：1996-08-06

申请号：US457704

申请日：1995-06-02

申请人： Manoj Kumar ,  Joseph M. Poplawski, Jr.

发明人： Manoj Kumar ,  Joseph M. Poplawski, Jr.

IPC分类号： G11C11/413 ,  G11C8/08 ,  G11C11/407 ,  G11C8/00 ,  H03K19/017

CPC分类号： G11C8/08

摘要： A word line driver circuit operable for receiving address signals from a decoder circuit and for gating these address signals to be outputted as a word line signal to one or more memory cells within a RAM. The driver circuit prevents oscillations of the outputted word line signal by not allowing any internal nodes between circuit elements to have a floating potential. This function is provided by a plurality of circuit elements arranged in a unique manner so that the internal nodes are not allowed to float.

摘要翻译： 字线驱动器电路，用于从解码器电路接收地址信号，并将这些地址信号选通作为字线信号输出到RAM内的一个或多个存储器单元。 驱动器电路通过不允许电路元件之间的任何内部节点具有浮动电位来防止输出的字线信号的振荡。 该功能由以独特方式布置的多个电路元件提供，使得内部节点不被允许浮动。