公开(公告)号：US20080258752A1

公开(公告)日：2008-10-23

申请号：US12147024

申请日：2008-06-26

申请人： Kanak B. Agarwal ,  Ying Liu ,  Chandler T. McDowell ,  Sani R. Nassif ,  James F. Plusquellic ,  Jayakumaran Sivagnaname

发明人： Kanak B. Agarwal ,  Ying Liu ,  Chandler T. McDowell ,  Sani R. Nassif ,  James F. Plusquellic ,  Jayakumaran Sivagnaname

IPC分类号： G01R31/26

CPC分类号： G01R31/3004 ,  G11C11/41 ,  G11C29/02 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5004 ,  G11C2029/5006

摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.

摘要翻译： 用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。 该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。 每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。 该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

公开(公告)号：US20080222579A1

公开(公告)日：2008-09-11

申请号：US11682450

申请日：2007-03-06

申请人： Kanak B. Agarwal ,  Ying Liu

发明人： Kanak B. Agarwal ,  Ying Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A moment-based method and system for evaluation of metal layer transient currents in an integrated circuit provides a computationally efficient evaluation of transient current magnitudes through each interconnect in the metal layer. The determinable magnitudes include peak, rms and average current, which can be used in subsequent reliability analyses. Interconnect path nodes are traversed and circuit moments are either retrieved from a previous interconnect delay analysis or are computed. For each pair of nodes, current moments are computed from the circuit moments. The average current is computed from the zero-order circuit moment and the peak and rms currents are obtained from expressions according to a lognormal or other distribution shape assumption for the current waveform at each node.

摘要翻译： 用于评估集成电路中金属层瞬态电流的基于瞬时的方法和系统提供了通过金属层中的每个互连的瞬态电流幅度的计算有效的评估。 可确定的幅度包括峰值，有效值和平均电流，可用于后续的可靠性分析。 互连路径节点被遍历，并且从先前的互连延迟分析中检索电路时刻，或者被计算。 对于每对节点，从电路时刻计算当前时刻。 平均电流是从零阶电路力矩计算的，峰值和均方根电流根据每个节点上的电流波形的对数正态分布形状假设的表达式获得。

公开(公告)号：US20080129326A1

公开(公告)日：2008-06-05

申请号：US12030140

申请日：2008-02-12

申请人： Kanak B. Agarwal ,  Sani R. Nassif

发明人： Kanak B. Agarwal ,  Sani R. Nassif

IPC分类号： G01R31/26

CPC分类号： G01R31/2884 ,  G01R31/2621 ,  G01R31/275

摘要： A characterization array circuit provides accurate threshold voltage distribution values for process verification and improvement. The characterization array includes a circuit for imposing a fixed drain-source voltage and a constant channel current at individual devices within the array. A circuit for sensing the source voltage of the individual device is also included within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.

摘要翻译： 表征阵列电路为过程验证和改进提供了准确的阈值电压分布值。 表征阵列包括用于在阵列内的各个器件处施加固定的漏源电压和恒定沟道电流的电路。 用于感测单个器件的源极电压的电路也包括在阵列内。 阈值电压的统计分布直接由源电压分布确定，通过将每个源极电压抵消通过完全表征阵列内的一个或多个器件而确定的值。 所得到的方法避免了对阵列内的每个器件进行表征的必要性，从而显着地减少了测量时间。

公开(公告)号：US20080120525A1

公开(公告)日：2008-05-22

申请号：US11560420

申请日：2006-11-16

申请人： Kanak B. Agarwal

发明人： Kanak B. Agarwal

IPC分类号： G01R31/3177 ,  G06F11/26

CPC分类号： G01R31/31816 ,  G01R31/318541 ,  G01R31/318569 ,  G06F11/1008

摘要： An error detection circuit for a latch precharges two dynamic nodes whose discharge paths are gated by true and complement storage nodes of the latch, such that one and only one of the dynamic nodes always discharges when the clock signal transitions from an active state to an inactive state. If a soft error flips the contents of the latch during storage mode the other dynamic node will discharge. A gate having inputs coupled to the dynamic nodes produces an error signal when both nodes have discharged. The error signal can then be used to select between true and complement outputs of the latch. The invention can be implemented in a more robust embodiment which examines the outputs of two error detection circuits to generate a combined error signal that ensures against false error detection when an upset occurs within one of the detection circuits.

摘要翻译： 用于锁存器的错误检测电路对两个动态节点进行预充电，其放电路径由锁存器的真实存储节点和补码存储节点门控，使得当时钟信号从活动状态转换到非活动状态时，动态节点中只有一个总是放电 州。 如果在存储模式期间软错误翻转锁存器的内容，则另一个动态节点将放电。 具有耦合到动态节点的输入的门在两个节点已经放电时产生误差信号。 然后，误差信号可用于在锁存器的真和输出之间进行选择。 本发明可以在更鲁棒的实施例中实现，该实施例检查两个错误检测电路的输出以产生组合误差信号，当在一个检测电路内发生不适时，确保防止错误检测。

公开(公告)号：US08824569B2

公开(公告)日：2014-09-02

申请号：US13313072

申请日：2011-12-07

申请人： Kanak B. Agarwal ,  Harm P. Hofstee ,  Damir A. Jamsek ,  Andrew K. Martin

发明人： Kanak B. Agarwal ,  Harm P. Hofstee ,  Damir A. Jamsek ,  Andrew K. Martin

IPC分类号： H04B1/66

CPC分类号： H03M7/30

摘要： Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.

公开(公告)号：US20140068529A1

公开(公告)日：2014-03-06

申请号：US13600319

申请日：2012-08-31

申请人： Kanak B. Agarwal ,  Shayak Banerjee

发明人： Kanak B. Agarwal ,  Shayak Banerjee

IPC分类号： G06F17/50

CPC分类号： G03F7/70441

摘要： A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a set of diffraction-orders, the IC layout including a set of features defined by a set of target edges, analyzing the diffraction pattern with a merit function to estimate printability of the IC layout, monitoring a change in value of the merit function as a position of at least one of the set of target edges is adjusted across a range, and retargeting the set of target edges based on the monitoring of the merit function.

摘要翻译： 公开了一种用于重新定位集成电路（IC）布局的计算机实现的方法。 在一个实施例中，该方法包括生成包括一组衍射级的IC布局的衍射图案，该IC布局包括由一组目标边缘定义的一组特征，用优点函数分析衍射图案以估计可印刷性 的IC布局，监视优值函数的值的变化作为所述一组目标边缘中的至少一个的位置在一个范围内被调整，并且基于所述优值函数的监视来重新定位所述一组目标边缘。

公开(公告)号：US20140049412A1

公开(公告)日：2014-02-20

申请号：US13587669

申请日：2012-08-16

申请人： Kanak B. Agarwal ,  Damir A. Jamsek ,  Michael A. Paolini ,  Robert B. Tremaine

发明人： Kanak B. Agarwal ,  Damir A. Jamsek ,  Michael A. Paolini ,  Robert B. Tremaine

IPC分类号： H03M7/30

CPC分类号： H03M7/30 ,  H03M7/607

摘要： In response to receipt of an input string, an attempt is made to identify, in a template store, a closely matching template for use as a compression template. In response to identification of a closely matching template that can be used as a compression template, the input string is compressed into a compressed string by reference to a longest common subsequence compression template. Compressing the input string includes encoding, in a compressed string, an identifier of the compression template, encoding substrings of the input string not having commonality with the compression template of at least a predetermined length as literals, and encoding substrings of the input string having commonality with the compression template of at least the predetermined length as a jump distance without reference to a base location in the compression template. The compressed string is then output.

摘要翻译： 响应于输入字符串的接收，尝试在模板存储器中识别紧密匹配的模板以用作压缩模板。 响应于可以用作压缩模板的紧密匹配的模板的识别，通过参考最长的公共子序列压缩模板将输入字符串压缩成压缩字符串。 压缩输入字符串包括在压缩字符串中编码压缩模板的标识符，将与压缩模板具有至少预定长度的压缩模板不一致的输入字符串的子串编码为文字，以及编码具有共同性的输入字符串的子串 至少具有预定长度的压缩模板作为跳跃距离，而不参考压缩模板中的基本位置。 然后输出压缩字符串。

公开(公告)号：US08594989B2

公开(公告)日：2013-11-26

申请号：US12420910

申请日：2009-04-09

申请人： Emrah Acar ,  Kanak B. Agarwal ,  Damir Jamsek ,  Sani R. Nassif

发明人： Emrah Acar ,  Kanak B. Agarwal ,  Damir Jamsek ,  Sani R. Nassif

IPC分类号： G06F17/50 ,  G06G7/62

CPC分类号： G06F17/5036

摘要： According to a method of simulation data processing, a difference is determined between a simulated value of a characteristic for a simulated integrated circuit device and a corresponding empirical value of the characteristic for a fabricated integrated circuit device. A data structure containing a simulation model of the fabricated integrated circuit device is accessed, where the data structure includes a plurality of entries each accessed via a unique index and an index used to access the data structure is offset in accordance with the difference between the simulated value and the empirical value. Operation of the simulated integrated circuit device is then simulated utilizing a value obtained from one of the plurality of entries of the data structure. Results of the simulation are stored in a data storage medium.

摘要翻译： 根据模拟数据处理的方法，在仿真集成电路器件的特性的模拟值与制造的集成电路器件的特性的对应经验值之间确定差异。 访问包含制造的集成电路器件的仿真模型的数据结构，其中数据结构包括通过唯一索引访问的多个条目，并且用于访问数据结构的索引根据模拟的 价值和经验价值。 然后使用从数据结构的多个条目之一获得的值来模拟仿真集成电路器件的操作。 模拟结果存储在数据存储介质中。

公开(公告)号：US08495530B2

公开(公告)日：2013-07-23

申请号：US13526984

申请日：2012-06-19

申请人： Kanak B. Agarwal

发明人： Kanak B. Agarwal

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape based on the amount and the direction of retargeting.

摘要翻译： 提供了用于光刻布局的电屈服增强重定向的机制。 对一组目标图案执行光学邻近校正，以便产生一组光学邻近校正掩模形状。 针对所述一组光学邻近校正掩模形状中的每一个生成一组光刻轮廓。 确定一组目标图案中的一组形状中的至少一种形状的电屈服敏感度。 还基于形状的电屈服敏感度来确定该组形状中的每个形状的重定向的量和方向。 基于重定向的数量和方向，为每个形状生成一组具有重定向边缘的目标模式。

公开(公告)号：US08402398B2

公开(公告)日：2013-03-19

申请号：US13157909

申请日：2011-06-10

申请人： Kanak B. Agarwal ,  Shayak Banerjee ,  Sani R. Nassif

发明人： Kanak B. Agarwal ,  Shayak Banerjee ,  Sani R. Nassif

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G03F1/70

摘要： A mechanism is provided for reducing through process delay variation in metal wires by layout retargeting. The mechanism performs initial retargeting, decomposition, and resolution enhancement techniques. For example, the mechanism may perform optical proximity correction. The mechanism then performs lithographic simulation and optical rules checking. The mechanism provides retargeting rules developed based on coupling lithography simulation and resistance/capacitance (RC) extraction. The mechanism performs RC extraction to capture non-linear dependency of RC on design shape dimensions. If the electrical properties in the lithographic simulation are within predefined specifications, the mechanism accepts the retargeting rules; however, if the electrical properties from RC extraction are outside the predefined specifications, the mechanism modifies the retargeting rules and repeats resolution enhancement techniques.

摘要翻译： 提供了一种通过布局重新定位来减少金属线中的工艺延迟变化的机制。 该机制执行初始重定向，分解和分辨率增强技术。 例如，该机构可以执行光学邻近校正。 该机制进行光刻模拟和光学规则检查。 该机制提供了基于耦合光刻模拟和电阻/电容（RC）提取开发的重定向规则。 该机制执行RC提取以捕获RC对设计形状尺寸的非线性依赖性。 如果光刻仿真中的电性能在预定义的规格范围内，则该机制接受重定向规则; 然而，如果来自RC提取的电性能超出预定义的规范，则该机制修改重定向规则并重复分辨率增强技术。