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    METHOD AND APPARATUS FOR ENCODING AND DECODING OF LOW DENSITY PARITY CHECK CODES
    72.
    发明申请
    METHOD AND APPARATUS FOR ENCODING AND DECODING OF LOW DENSITY PARITY CHECK CODES 审中-公开
    用于编码和解码低密度奇偶校验码的方法和装置

    公开(公告)号：US20140372825A1

    公开(公告)日：2014-12-18

    申请号：US14303834

    申请日：2014-06-13

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hong-sil JEONG ,  Se-ho MYUNG ,  Kyung-joong KIM

    IPC分类号： H03M13/11

    CPC分类号： H03M13/1165 ,  H03M13/036 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2906 ,  H03M13/6552

    摘要： An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.

    摘要翻译： 提供一种编码装置。 该编码包括：低密度奇偶校验（LDPC）编码器，其基于奇偶校验矩阵对输入比特执行LDPC编码，以生成由64,800比特形成的LDPC码字，其中奇偶校验矩阵包括信息字子矩阵 和奇偶校验子矩阵，信息字子矩阵由每个包括360列的多个列块的组形成，并且奇偶校验矩阵和信息字子矩阵由表示位置的各种表定义 的价值一（1）存在于每第360列。

    TRANSMITTER AND SHORTENING METHOD THEREOF
    73.
    发明公开
    TRANSMITTER AND SHORTENING METHOD THEREOF 审中-公开

    公开(公告)号：US20230299876A1

    公开(公告)日：2023-09-21

    申请号：US18201430

    申请日：2023-05-24

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hong-sil JEONG ,  Kyung-Joong KIM ,  Se-ho MYUNG

    IPC分类号： H04L1/00 ,  H03M13/11 ,  H03M13/15 ,  H03M13/25 ,  H03M13/29 ,  H03M13/00

    CPC分类号： H04L1/0041 ,  H03M13/1102 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/253 ,  H03M13/255 ,  H03M13/2906 ,  H03M13/618 ,  H04L1/0057

    摘要： A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, determine whether a number of the outer-encoded bits satisfies a predetermined number of bits required according to at least one of a code rate and a code length for Low Density Parity Check (LDPC) encoding, pads zero bits to some of the bits in the bit groups if the number of the outer-encoded bits is less than the predetermined number of bits, and maps the outer-encoded bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute LDPC information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the some of the bits, in which zero bits are padded, are included in some of the bit groups which are not sequentially disposed in the LDPC information bits.

    TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF
    76.
    发明申请
    TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF 有权

    公开(公告)号：US20220398157A1

    公开(公告)日：2022-12-15

    申请号：US17882217

    申请日：2022-08-05

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Se-ho MYUNG ,  Hong-sil Jeong ,  Kyung-joong Kim

    IPC分类号： G06F11/10 ,  G06F17/11

    摘要： A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

    TRANSMITTER AND SEGMENTATION METHOD THEREOF
    77.
    发明申请
    TRANSMITTER AND SEGMENTATION METHOD THEREOF 有权

    公开(公告)号：US20220149869A1

    公开(公告)日：2022-05-12

    申请号：US17583458

    申请日：2022-01-25

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hong-sil JEONG ,  Kyung-Joong KIM ,  Se-ho MYUNG

    IPC分类号： H03M13/27 ,  H03M13/11

    摘要： A transmitter is provided. The transmitter includes: a segmenter configured to segment information bits into a plurality of blocks based on one of a plurality of preset reference values; an outer encoder configured to encode each of the plurality of blocks to generate first parity bits; and a Low Density Parity Check (LDPC) encoder configured to encode each of the plurality of blocks and the first parity bits to generate an LDPC codeword including second parity bits, wherein the one of the preset reference values is determined depending on at least one of a code rate used to encode each of the plurality of blocks and the first parity bits and whether to perform repetition of at least a part of the LDPC codeword in the LDPC codeword.

    TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF
    78.
    发明申请
    TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF 有权

    公开(公告)号：US20210336637A1

    公开(公告)日：2021-10-28

    申请号：US17333101

    申请日：2021-05-28

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Se-ho MYUNG ,  Hong-sil JEONG ,  Kyung-joong KIM

    IPC分类号： H03M13/27 ,  H03M13/25 ,  H03M13/03 ,  H03M13/11 ,  H03M13/15 ,  H03M13/29

    摘要： A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns including a plurality of rows, respectively, and comprises: a block interleaver configured to divide each of the plurality of columns into a first part and a second part, and interleave a plurality of bit groups constituting the LDPC codeword, all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part, at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns constituting the second part.