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    Deep neural network implementation for soft decoding of BCH code
    2.
    发明授权
    Deep neural network implementation for soft decoding of BCH code 有权

    公开(公告)号：US12050514B1

    公开(公告)日：2024-07-30

    申请号：US18184872

    申请日：2023-03-16

    申请人： Kioxia Corporation

    发明人： Avi Steiner ,  Ofir Kanter

    IPC分类号： G06F11/10 ,  H03M13/15

    CPC分类号： G06F11/1068 ,  H03M13/152

    摘要： Systems, methods, non-transitory computer-readable media to perform operations associated with the storage medium. One system includes a storage medium and an encoding/decoding (ED) system to perform operations associated with the storage medium, the ED system being configured to process a set of log-likelihood ratios (LLRs) and a syndrome vector to obtain a set of confidence values for each bit of a codeword, estimate an error vector based on selecting one or more bit locations with confidence values from the set of confidence values above threshold value and applying hard decision decoding to the selected one or more bit locations, calculate a sum LLR score for the estimated error vector, and output a decoded codeword based on the estimated error vector and the sum LLR score.

    Error correction for internal read operations
    5.
    发明授权
    Error correction for internal read operations 有权

    公开(公告)号：US11789817B2

    公开(公告)日：2023-10-17

    申请号：US17240471

    申请日：2021-04-26

    申请人： Micron Technology, Inc.

    发明人： Robert B. Eisenhuth

    IPC分类号： G06F11/10 ,  H03M13/15 ,  G06F11/00 ,  G06F3/06

    CPC分类号： G06F11/1076 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  H03M13/152 ,  H03M13/1515

    摘要： Methods, systems, and devices for error correction for internal read operations are described. In some memory systems, a memory device may perform an internal read operation, in which the memory device reads data internal to the memory device (e.g., without sending the data to a memory system controller). To detect and correct errors during an internal read operation, the memory device may use an error control circuit on a memory die. The error control circuit on the memory die may operate on the same codeword, including the same data and same parity bits, as an error control circuit at the memory system controller, effectively reusing the stored parity bits for host read operations and internal read operations. To reduce the decoding overhead at the memory device, the error control circuit on the memory die may support detecting fewer errors than the error control circuit at the memory system controller.

    Encoding Method and Apparatus
    6.
    发明公开
    Encoding Method and Apparatus 审中-公开

    公开(公告)号：US20230308117A1

    公开(公告)日：2023-09-28

    申请号：US18176217

    申请日：2023-02-28

    申请人： Huawei Technologies Co., Ltd.

    发明人： Huazi Zhang ,  Xianbin Wang ,  Jiajie Tong ,  Shengchen Dai ,  Rong Li ,  Jun Wang

    IPC分类号： H03M13/15 ,  H03M13/00

    CPC分类号： H03M13/152 ,  H03M13/616 ,  H03M13/6362

    摘要： An encoding method and apparatus are provided, to propose a construction and encoding scheme of a BCH code. A code length and a code rate of an obtained BCH code are flexible, to satisfy a requirement of flexible channel encoding in wireless communication. The method includes determining a first encoding parameter based on a first BCH code, where the first BCH code is a to-be-coded BCH code, the first encoding parameter is a first code or a generator matrix of a first code, the first code has a code length of n and an information bit length of k, n is greater than o, and k is greater than o, and performing BCH encoding based on the first encoding parameter.