公开(公告)号：US20080062795A1

公开(公告)日：2008-03-13

申请号：US11517674

申请日：2006-09-08

申请人： Shine Chung

发明人： Shine Chung

IPC分类号： G11C11/24 ,  G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4099 ,  G11C2207/2227

摘要： This invention discloses a dynamic random access memory (DRAM) device comprising a first bit-line coupled to a first terminal of at least one memory cell capacitor through one or more pass transistors, a second bit-line coupled to a first terminal of at least one reference cell capacitor through one or more pass transistors, and a cell plate connected to both a second terminal of at least one memory cell capacitor and a second terminal of at least one reference cell capacitor, wherein the cell plate is biased at approximately one half of a voltage difference between a positive supply voltage (Vdd) and a complementary lower supply voltage (Vss), and wherein the reference cell capacitor does not store any charge prior to a reading operation, and wherein both the first and second bit-lines are pre-charged to either Vdd or Vss prior to the reading operation.

公开(公告)号：US20070279816A1

公开(公告)日：2007-12-06

申请号：US11839966

申请日：2007-08-16

申请人： Shine Chung ,  Jiann-Tseng Huang ,  Shao-Chang Huang

发明人： Shine Chung ,  Jiann-Tseng Huang ,  Shao-Chang Huang

IPC分类号： H02H9/04 ,  H03K19/003

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A method and system is disclosed for protecting electrical fuse circuitry. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.

摘要翻译： 公开了一种用于保护电熔丝电路的方法和系统。 具有静电放电（ESD）保护的电熔丝电路具有至少一个电熔丝，与至少一晶体管串联耦合的编程装置，用于接收用于控制流经电熔丝的编程电流的控制信号， 电压源耦合到熔丝和用于提供编程电流的编程装置，以及保护模块，其在其第一端耦合到晶体管的栅极，以减少由于到达电压的电静电而在晶体管的栅极处累积的电荷 源，从而防止编程设备意外编程保险丝。

公开(公告)号：US20060238220A1

公开(公告)日：2006-10-26

申请号：US11111281

申请日：2005-04-20

申请人： Shine Chung ,  Cliff Hou ,  Mark Chen ,  Lee-Chung Lu

发明人： Shine Chung ,  Cliff Hou ,  Mark Chen ,  Lee-Chung Lu

IPC分类号： H03K19/0175

CPC分类号： G06F17/505

摘要： A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.

摘要翻译： 公开了一种在基于单元的设计中利用混合的低阈值电压（低Vt）和高阈值电压（高Vt）装置的方法，从而可以实现电路速度和功率性能的折衷。 使用具有不均匀阈值器件的电池来设计电路，速度或/和功率优化与完全定制的设计相当。

公开(公告)号：US20050212567A1

公开(公告)日：2005-09-29

申请号：US10808122

申请日：2004-03-24

申请人： Yue-Der Chih ,  Shine Chung

发明人： Yue-Der Chih ,  Shine Chung

IPC分类号： H03B1/00 ,  H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/00315

摘要： A high voltage switch circuit is disclosed for reducing high voltage junction stresses. The circuit contains a cascode device structure having one or more transistors of a same type connected in a series and being operable with a normal operating voltage and a high operating voltage. The cascode device structure comprises a high operating voltage coupled to a first end of the device structure, a low voltage coupled to a second end, and one or more control voltages controllably coupled to the gates of the transistors, wherein at least one of the control voltages coupled to the gate of at least one transistor is raised to a medium voltage level that is higher than a normal operating voltage when operating under the high operating voltage for tolerating stress imposed thereon by the high operating voltage.

摘要翻译： 公开了一种用于降低高压结应力的高压开关电路。 该电路包含具有一个或多个相同类型的晶体管的共源共栅器件结构，其串联连接并可与正常工作电压和高工作电压一起工作。 共射共同体装置结构包括耦合到器件结构的第一端的高工作电压，耦合到第二端的低电压以及可控地耦合到晶体管的栅极的一个或多个控制电压，其中至少一个控制 耦合到至少一个晶体管的栅极的电压在高工作电压下操作时升高到高于正常工作电压的中等电压电平，以容忍由高工作电压施加在其上的应力。

公开(公告)号：US5894427A

公开(公告)日：1999-04-13

申请号：US968565

申请日：1997-11-12

申请人： Shine Chung

发明人： Shine Chung

IPC分类号： G06F7/02 ,  G06F5/01

CPC分类号： G06F7/02 ,  G06F2207/025

摘要： A technique for concurrently detecting a repetitive occurrence of a bit pattern in a bit string. Successive bits of the bit string are separated into bit groupings and the combined bits are analyzed for the presence of the bit pattern. The logic for subsequent analysis to reduce the number of groupings is achieved by the use of a hierarchically decreasing logic array. At each level of the hierarchy, the bit analysis is reduced until a final output is reached. This final output provides state and address outputs for identifying the detection of the bit pattern occurrences and the address where the bit patterns occur.

摘要翻译： 一种用于同时检测比特串中的比特模式的重复出现的技术。 比特串的连续比特被分成比特分组，并且针对比特模式的存在来分析组合的比特。 用于减少分组数量的后续分析的逻辑是通过使用分级递减的逻辑阵列来实现的。 在层次结构的每个级别，位分析被减少，直到达到最终输出。 该最终输出提供用于识别位模式发生的检测和位模式发生的地址的状态和地址输出。

公开(公告)号：US5774710A

公开(公告)日：1998-06-30

申请号：US710560

申请日：1996-09-19

申请人： Shine Chung

发明人： Shine Chung

IPC分类号： G06F9/38

CPC分类号： G06F9/3806

摘要： A microprocessor includes an instruction cache and a branch target buffer to implement a branch prediction scheme. The instruction cache, which stores branch instructions, is organized into cache lines and sets to implement set associative caching with memory that stores instructions. The branch target buffer includes storage locations organized into lines such that instructions stored in a cache line of the instruction cache correspond to a line in the branch target buffer. The storage locations permit storage of a branch target address that corresponds to any one of the sets in the cache line of the instruction cache to permit storage of branch information for multiple branch instructions when a cache line of a set stores more than one branch instruction. Thus, the resources of the branch target buffer are shared among the sets of the instruction cache.

摘要翻译： 微处理器包括指令高速缓存和分支目标缓冲器以实现分支预测方案。 存储分支指令的指令高速缓存组织成高速缓存行和集合，以与存储指令的存储器一起实现集合关联缓存。 分支目标缓冲器包括组织成行的存储位置，使得存储在指令高速缓存行中的指令对应于分支目标缓冲器中的一行。 当集合的高速缓存行存储多于一个分支指令时，存储位置允许存储对应于指令高速缓存的高速缓存行中的任何一个集合的分支目标地址以允许多个分支指令的分支信息的存储。 因此，分支目标缓冲器的资源在指令高速缓存的组之间被共享。

公开(公告)号：US08476949B2

公开(公告)日：2013-07-02

申请号：US11470019

申请日：2006-09-05

申请人： Shine Chung ,  Kenneth Chiakun Weng ,  Pin-Lin Chiu

发明人： Shine Chung ,  Kenneth Chiakun Weng ,  Pin-Lin Chiu

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H01L29/0847 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7833 ,  H01L29/7835

摘要： An edge triggered flip-flop circuit is disclosed with a clock signal, an input signal, a switch module using the clock signal for defining a data passing window, and a latch module for receiving the input signal during the data passing window.

摘要翻译： 公开了一种边沿触发触发器电路，其具有时钟信号，输入信号，使用用于定义数据传递窗口的时钟信号的开关模块，以及用于在数据传递窗口期间接收输入信号的锁存模块。

公开(公告)号：US20120243290A1

公开(公告)日：2012-09-27

申请号：US13492635

申请日：2012-06-08

申请人： Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsueh

发明人： Yung-Lung Lin ,  Jui-Jen Wu ,  Shine Chung ,  Fu-Lung Hsueh

IPC分类号： G11C17/16

CPC分类号： G11C11/5692 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

摘要翻译： 一种用于编程多电平电熔丝系统的方法包括：提供具有电熔丝的保险丝盒，并向所述电熔丝提供至少两个熔丝写入电压中的一个，以将所述电熔丝编程为至少两个电阻状态之一。 保险丝盒包括至少一个电熔丝，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并配置成产生两个或多个电压电平的可变电源。

公开(公告)号：US08030181B2

公开(公告)日：2011-10-04

申请号：US12881944

申请日：2010-09-14

申请人： Shine Chung ,  Fu-Lung Hsueh ,  Fu-Chieh Hsu

发明人： Shine Chung ,  Fu-Lung Hsueh ,  Fu-Chieh Hsu

IPC分类号： H01L21/326

CPC分类号： G11C17/18

摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.

摘要翻译： 公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接， 以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流 保险丝编程操作。

公开(公告)号：US07852686B2

公开(公告)日：2010-12-14

申请号：US12062320

申请日：2008-04-03

申请人： Shine Chung ,  Jonathan Hung

发明人： Shine Chung ,  Jonathan Hung

IPC分类号： G11C16/04

CPC分类号： G11C11/4091 ,  G11C7/062

摘要： A circuit and method for a sense amplifier for sensing the charge stored when a select signal couples a memory cell to the sense amplifier. A pull up voltage and a pull down voltage are instantaneously supplied to the sense amplifier to sense the small signal differential input on the complementary bit lines and to simultaneously restore the value stored in the memory cell. A differential output signal generator circuit is provided to instantaneously supply the pull up and pull down voltages. In another preferred embodiment the signal generator provides the pull up and pull down voltages at a first level and subsequently increases the pull up voltage to a voltage greater than the positive supply voltage and decreases the pull down voltage. A method of sensing is disclosed wherein the sense and restore actions are performed instantaneously to provide memory cell sensing with greater tolerance of device mismatches.

摘要翻译： 一种用于感测放大器的电路和方法，用于感测当选择信号将存储器单元耦合到感测放大器时所存储的电荷。 立即将上拉电压和下拉电压提供给读出放大器以感测互补位线上的小信号差分输入，并同时恢复存储在存储单元中的值。 提供差分输出信号发生器电路以瞬时提供上拉和下拉电压。 在另一优选实施例中，信号发生器在第一电平上提供上拉和下拉电压，随后将上拉电压增加到大于正电源电压的电压并降低下拉电压。 公开了一种感测方法，其中感测和恢复动作被立即执行以提供具有更大的设备不匹配容限的存储器单元感测。