公开(公告)号：US06742174B1

公开(公告)日：2004-05-25

申请号：US10037844

申请日：2001-10-19

申请人： Kuang-Chien Chen ,  Chih-Chang Lin ,  Cheng-Ta Hsieh ,  Yifeng Wang

发明人： Kuang-Chien Chen ,  Chih-Chang Lin ,  Cheng-Ta Hsieh ,  Yifeng Wang

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method for modeling a circuit design includes synthesizing the circuit design to create a first gate-level representation of the circuit design. The method also includes analyzing a second gate-level representation of the circuit design to learn architecture information, and resynthesizing the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design. A computer-readable storage medium has stored thereon computer instructions that, when executed by a computer, cause the computer to synthesize a circuit design to create a first gate-level representation of the circuit design. The computer instructions also cause the computer to analyze a second gate-level representation of the circuit design to learn architecture information, and resynthesize the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design.

摘要翻译： 用于对电路设计进行建模的方法包括合成电路设计以创建电路设计的第一门级表示。 该方法还包括分析电路设计的第二门级表示以学习架构信息，以及重新合成电路设计的第一门级表示，以从电路设计的第二门级表示中并入所学习的体系结构信息。 计算机可读存储介质上存储有计算机指令，其在由计算机执行时使计算机合成电路设计以创建电路设计的第一门级表示。 计算机指令还使得计算机分析电路设计的第二门级表示以学习架构信息，并重新合成电路设计的第一门级表示，以将来自第二门级表示的学习架构信息 电路设计。

公开(公告)号：US20080127014A1

公开(公告)日：2008-05-29

申请号：US11586879

申请日：2006-10-25

申请人： Manish Pandey ,  Rajat Arora ,  Chih-Chang Lin ,  Huan-Chih Tsai ,  Bharat Chandramouli ,  Kei-Yong Khoo

发明人： Manish Pandey ,  Rajat Arora ,  Chih-Chang Lin ,  Huan-Chih Tsai ,  Bharat Chandramouli ,  Kei-Yong Khoo

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.

摘要翻译： 公开了低功率设计的等效性检验方法和系统。 该方法包括接收电路的寄存器传送级（RTL）网表表示，接收用于描述电路的功率需求的功率指定文件，创建用于表示使用RTL网表的电路的设计实现的低功率门网表，以及 电源规范文件，创建用于表示使用RTL网表和电源规格文件的电路的设计规范的参考低功率RTL网表，以及执行低功率门网表和参考低功率RTL网表之间的等价检查。 该方法还包括将电力规范文件中描述的低功率信息注释到参考低功率RTL网表中，以及在参考低功率RTL网表中创建低功率逻辑。

公开(公告)号：US20050174013A1

公开(公告)日：2005-08-11

申请号：US11100556

申请日：2005-04-07

申请人： Chin-Wen Chou ,  Eddie Cheng ,  K. Wu ,  Chih-Chang Lin

发明人： Chin-Wen Chou ,  Eddie Cheng ,  K. Wu ,  Chih-Chang Lin

IPC分类号： H01L41/04 ,  H01L41/107 ,  H02M7/217 ,  H05B41/282

CPC分类号： H01L41/044 ,  H02M3/158 ,  H05B41/2828 ,  Y02B70/1425

摘要： A transformer level driving circuit mainly aims to drive a medium voltage system. It includes a control unit to generate a resonant frequency and output phase signal waveforms, and a medium voltage driving circuit which includes a floating level unit and a driving unit which receives a medium voltage electric input. The driving unit actuates opening and closing at different time to enable the floating level unit to output a voltage floating level thereby to drive a ceramic transformer to control the medium voltage system through a low voltage level.

摘要翻译： 变压器电平驱动电路主要用于驱动中压系统。 它包括一个产生谐振频率和输出相位信号波形的控制单元，以及包括一个浮置电平单元和一个接收中压电输入的驱动单元的中压驱动电路。 驱动单元在不同时间启动打开和关闭，以使浮动水平单元能够输出电压浮动电平，从而驱动陶瓷变压器以通过低电压电平控制中压系统。

公开(公告)号：US06842884B2

公开(公告)日：2005-01-11

申请号：US10230976

申请日：2002-08-28

申请人： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

发明人： Yung-Te Lai ,  Chioumin Chang ,  Kung-Chien Chen ,  Chih-Chang Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/504

摘要： An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuits are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.

摘要翻译： 等价检查方法提供第一和第二逻辑功能。 不要在第一和第二逻辑功能中插入无门的条件。 无关门的插入产生第一中间电路和第二中间电路。 当3DC门和SDC门共存在第一和第二中间电路中时，第一中间电路的所有3DC门被传播并合并成单个3DC门。 当3DC门和SDC门共存在第一和第二中间电路中时，第二中间电路的所有3DC门都被传播并合并成单个3DC门。 响应于3DC门的传播和合并产生第一和第二电路。 然后在不同的等价关系下对第二电路执行第一电路的组合等价检查。