公开(公告)号：US07441471B1

公开(公告)日：2008-10-28

申请号：US11610398

申请日：2006-12-13

申请人： John D. Davis

发明人： John D. Davis

IPC分类号： G01L5/04 ,  G01L1/26 ,  E02D5/74 ,  E21D20/00

CPC分类号： E21B7/005 ,  E02D5/801 ,  E02D7/22 ,  E02D33/00 ,  G01L5/0038

摘要： A ground anchor load testing system includes a ground anchoring unit having a bare upper drill shaft portion along and around which a reaction anchor with its hollow shaft is temporary installed. During test loading of the installed ground anchoring unit, a test loading head is coupled with both concentric flanging ends of the ground anchoring unit and the temporarily installed reaction anchor. The test loading head exerts via a first coupling the push test load on the first flanging end of the ground anchoring unit while withholding itself via a second coupling on the second flanging end of the reaction anchor. A measurement device may be positioned on the ground adjacent the test load head. Eventual axial displacement of the ground anchoring unit under test load may be externally recognized by the measurement device via an axial displacement indicator in axial connection with the first coupling.

摘要翻译： 地面锚固载荷测试系统包括一个地面锚定单元，该地面锚固单元具有裸露的上部钻杆轴部分，并且围绕着该中心轴的反作用锚临时安装。 在安装的地面锚固单元的测试加载期间，测试装载头与地面锚固单元的两个同心的凸缘端和临时安装的反作用锚连接。 测试装载头通过第一联接器将推动测试载荷施加在地面锚固单元的第一凸缘端上，同时通过反应锚的第二翻边端上的第二联接件自身保持自身。 测量装置可以位于与测试负载头相邻的地面上。 接地锚固单元在试验载荷下的最终轴向位移可以由测量装置经由与第一联轴器轴向连接的轴向位移指示器而被外部识别。

公开(公告)号：US06448576B1

公开(公告)日：2002-09-10

申请号：US09943178

申请日：2001-08-30

申请人： John D. Davis ,  Thomas J. McIntyre ,  John C. Rodgers ,  Keith K. Sturcken ,  Peter W. Spreen ,  Tushar K. Shah

发明人： John D. Davis ,  Thomas J. McIntyre ,  John C. Rodgers ,  Keith K. Sturcken ,  Peter W. Spreen ,  Tushar K. Shah

IPC分类号： H01L2904

CPC分类号： H01L23/5256 ,  G11C13/0004 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

摘要翻译： 公开了一种在半导体器件内制造可编程硫族化物保险丝的方法。 最初在基板上形成电阻器。 然后，在电阻器的顶部形成硫族化物保险丝。 最后，导电层沉积在硫族化物保险丝的顶部，以提供对硫族化物保险丝的电导通。

公开(公告)号：US4833425A

公开(公告)日：1989-05-23

申请号：US173517

申请日：1988-03-25

申请人： Edward F. Culican, Sr. ,  John D. Davis ,  John F. Ewen ,  Scott A. Mc Cabe ,  Joseph M. Mosley ,  Allan L. Mullgrav, Jr. ,  Philip F. Noto ,  Clarence I. Peterson, Jr. ,  Philip E. Pritzlaff, Jr.

发明人： Edward F. Culican, Sr. ,  John D. Davis ,  John F. Ewen ,  Scott A. Mc Cabe ,  Joseph M. Mosley ,  Allan L. Mullgrav, Jr. ,  Philip F. Noto ,  Clarence I. Peterson, Jr. ,  Philip E. Pritzlaff, Jr.

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/099 ,  H03L7/23

CPC分类号： H01L27/118 ,  H03K19/003 ,  H03L7/07 ,  H03L7/0995 ,  H03L7/23

摘要： A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.