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公开(公告)号：US10658173B2
公开(公告)日：2020-05-19
申请号：US16039284
申请日：2018-07-18
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Ching-Pin Hsu
IPC: H01L21/02 , H01L21/3213 , H01L21/67 , H01L21/3065 , H01L27/108
Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.
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公开(公告)号：US10600749B2
公开(公告)日：2020-03-24
申请号：US16505724
申请日：2019-07-09
Inventor： Feng-Yi Chang , Fu-Che Lee , Chin-Hsin Chiu
IPC: H01L21/768 , H01L23/00 , H01L21/66 , H01L23/525 , H01L23/62 , H01L23/532 , H01L23/485 , H01L23/528 , H01L21/311 , H01L23/31
Abstract: A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.
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公开(公告)号：US20200083325A1
公开(公告)日：2020-03-12
申请号：US16154704
申请日：2018-10-08
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/06 , H01L21/027 , H01L29/66 , H01L21/033 , H01L21/311 , H01L21/3213
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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公开(公告)号：US20200043733A1
公开(公告)日：2020-02-06
申请号：US16136265
申请日：2018-09-20
Inventor： Feng-Yi Chang , Yu-Cheng Tung , Fu-Che Lee
IPC: H01L21/033 , H01L27/108
Abstract: A semiconductor device and a method of forming the same, the semiconductor includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.
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公开(公告)号：US10535610B2
公开(公告)日：2020-01-14
申请号：US16003090
申请日：2018-06-07
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Wang Zhan , Chia-Liang Liao , Yu-Cheng Tung , Chien-Hao Chen , Chia-Hung Wang
IPC: H01L23/544 , H01L27/108 , H01L21/311
Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.
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Patent Agency Ranking
公开(公告)号：US10535530B2
公开(公告)日：2020-01-14
申请号：US16167435
申请日：2018-10-22
Inventor： Feng-Yi Chang , Fu-Che Lee , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L21/308 , H01L21/033 , H01L21/8234
Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.
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公开(公告)号：US20190318930A1
公开(公告)日：2019-10-17
申请号：US15975730
申请日：2018-05-09
Inventor： Feng-Yi Chang , Fu-Che Lee , Hsin-Yu Chiang
IPC: H01L21/033 , H01L21/311
Abstract: A patterning method includes the following steps. A second mask layer is formed on a first mask layer. A patterning process is performed to the first mask layer and the second mask layer. The first mask layer is patterned to be a first mask pattern, and the second mask layer is patterned to be a second mask pattern formed on the first mask pattern. A first trim process is performed to the second mask pattern. A width of the second mask pattern is smaller than a width of the first mask pattern after the first trim process. A cover layer is formed covering the first mask pattern and the second mask pattern after the first trim process, and an etching process is performed to the first mask pattern after the step of forming the cover layer.
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公开(公告)号：US10446554B2
公开(公告)日：2019-10-15
申请号：US16027267
申请日：2018-07-04
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen
IPC: G11C11/404 , H01L27/108 , H01L49/02 , G11C11/4074 , G11C7/02
Abstract: A semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.
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公开(公告)号：US20190304909A1
公开(公告)日：2019-10-03
申请号：US16446590
申请日：2019-06-19
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Fu-Che Lee , Chien-Cheng Tsai , Feng-Ming Huang
IPC: H01L23/528 , H01L29/06 , H01L21/762 , H01L27/108 , H01L21/311 , H01L21/768 , H01L23/522
Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
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公开(公告)号：US20190304777A1
公开(公告)日：2019-10-03
申请号：US15964031
申请日：2018-04-26
Inventor： Feng-Yi Chang , Fu-Che Lee , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L21/02 , H01L21/033
Abstract: The present invention provides a method for fabricating a hard mask, comprising: firstly, a first material layer and a second material layer are provided on the first material layer, a cell region and a peripheral region are defined thereon, and then a plurality of sacrificial patterns and a plurality of spacers are formed in the cell region on the second material layer, each two spacers are located at two sides of each of the sacrificial patterns. Afterwards, a first etching step is performed to remove the sacrificial patterns, a second etching step is performed to remove a portion of the second material layer and expose a portion of the first material layer within the cell region, and a third etching step is performed to remove portions of the first material layer, so as to forma plurality of first recesses in the first material layer.
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