LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices
    71.
    发明申请
    LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices 失效
    具有用CSI(循环移位身份)和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC(低密度奇偶校验)码

    公开(公告)号:US20090327847A1

    公开(公告)日:2009-12-31

    申请号:US12533306

    申请日:2009-07-31

    IPC分类号: G06F11/10

    摘要: LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

    摘要翻译: 具有用CSI(循环移位身份)和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC(低密度奇偶校验)码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成,并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI(循环移位身份)子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上,另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵(即,其中的所有元素为零“0”)。

    FIXED-SPACING PARITY INSERTION FOR FEC (FORWARD ERROR CORRECTION) CODEWORDS
    72.
    发明申请
    FIXED-SPACING PARITY INSERTION FOR FEC (FORWARD ERROR CORRECTION) CODEWORDS 有权
    用于FEC(前向纠错)编码的固定间隔奇偶校验插入

    公开(公告)号:US20090193312A1

    公开(公告)日:2009-07-30

    申请号:US12021911

    申请日:2008-01-29

    IPC分类号: H04L1/18

    摘要: Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order of the parity bits may be changed before they are placed into the codeword. Moreover, the order of the information bits may also be modified before they are placed into the codeword. The FEC encoding employed to generate the parity bits from the information bits can be any of a variety of codes include Reed-Solomon (RS) code, LDPC (Low Density Parity Check) code, turbo code, turbo trellis coded modulation (TTCM), or some other code providing FEC capabilities.

    摘要翻译: 用于FEC(前向纠错)码字的固定间隔奇偶校验插入。 当产生码字时,使用固定间隔来分散信息比特之间的奇偶比特。 根据该固定间隔,在码字中的每个奇偶校验位之间放置相同数量的信息比特。 如果需要,奇偶校验位的顺序可以在它们被置入码字之前改变。 此外,信息比特的顺序也可以在它们被置入码字之前被修改。 用于从信息比特生成奇偶校验位的FEC编码可以是各种代码中的任何一种,包括里德 - 所罗门(RS)码,LDPC(低密度奇偶校验)码,turbo码,turbo格状编码调制(TTCM) 或提供FEC能力的一些其他代码。

    Low Density Parity Check (LDPC) Encoded Higher Order Modulation
    73.
    发明申请
    Low Density Parity Check (LDPC) Encoded Higher Order Modulation 有权
    低密度奇偶校验(LDPC)编码高阶调制

    公开(公告)号:US20090129484A1

    公开(公告)日:2009-05-21

    申请号:US12272556

    申请日:2008-11-17

    IPC分类号: H04L27/36 H04N7/24

    摘要: A method and apparatus is disclosed to map a sequence of data to Quadrature Amplitude Modulation (QAM) constellation symbols. The method and apparatus encodes only a portion of the sequence of data and leaves a remaining portion of the sequence of data unencoded. The encoded portion of the sequence of data and the remaining unencoded portion of the sequence of data are then mapped into modulation symbols of the QAM constellation. The encoded portion of the sequence of data selects subsets of the QAM constellation, and the remaining unencoded portion of the sequence of data determines a specific modulation symbol within each subset of the QAM constellation.

    摘要翻译: 公开了一种将数据序列映射到正交幅度调制(QAM)星座符号的方法和装置。 该方法和装置仅对该数据序列的一部分进行编码,并留下未被编码的数据序列的剩余部分。 然后将数据序列的编码部分和数据序列的剩余未编码部分映射到QAM星座图的调制符号中。 数据序列的编码部分选择QAM星座的子集,并且数据序列的剩余未编码部分确定QAM星座图的每个子集内的特定调制符号。

    Symbol by symbol variable code rate capable communication device
    74.
    发明授权
    Symbol by symbol variable code rate capable communication device 有权
    符号可变码率符号符号通讯装置

    公开(公告)号:US07472335B1

    公开(公告)日:2008-12-30

    申请号:US10338185

    申请日:2003-01-08

    IPC分类号: H03M13/03

    摘要: Symbol by symbol variable code rate capable communication device. A communication device is operable to perform processing of a variable code rate signal whose code rate varies on a symbol by symbol basis. This may involve performing encoding of input to generate the variable code rate signal; alternatively, this may involve performing decoding of a variable code rate signal. In doing so, this approach may involve using a single encoder and/or decoder (depending on the application). In some instances, a single device is operable to encode a first variable code rate signal (for transmission to another device) and to decode a second variable code rate signal (that has been received from another device). In addition, a method of coding (including one or both of encoding and decoding) may also operate of a variable code rate signal whose code rate varies on a symbol by symbol basis.

    摘要翻译: 符号可变码率符号符号通讯装置。 通信装置可操作以执行码率根据符号依次变化的可变码率信号的处理。 这可以涉及执行输入的编码以生成可变码率信号; 或者,这可能涉及执行可变码率信号的解码。 在这样做时,该方法可能涉及使用单个编码器和/或解码器(取决于应用)。 在一些情况下,单个设备可操作地对第一可变码率信号(用于传输到另一设备)进行编码并对第二可变码率信号(已从另一设备接收到的信号)进行解码。 此外,编码(包括编码和解码中的一个或两个)的方法也可以对码率根据符号依次变化的可变码率信号进行操作。

    Quadratic polynomial permutation (QPP) interleaver providing hardware savings and flexible granularity adaptable to any possible turbo code block size
    75.
    发明申请
    Quadratic polynomial permutation (QPP) interleaver providing hardware savings and flexible granularity adaptable to any possible turbo code block size 有权
    二次多项式置换(QPP)交织器,提供硬件节省和灵活的粒度,适用于任何可能的turbo码块大小

    公开(公告)号:US20080172590A1

    公开(公告)日:2008-07-17

    申请号:US11810890

    申请日:2007-06-07

    IPC分类号: H03M13/03

    摘要: Quadratic polynomial permutation (QPP) interleaver providing hardware saving and flexible granularity adaptable to any possible turbo code block size. A means is presented by which only a very small number of coefficients need be stored to effectuate a wide variety of QPP interleaves as can be employed in the context of turbo coding. In one instance, to accommodate the approximate 6000 different turbo code block sizes in 3GPP LTE channel coding, only 5 different coefficient values need to be stored to effectuate a very broad range of QPP interleaves to be applied each of those various turbo code block sizes. Moreover, a few small number of dummy bits, if any, need to be employed to accommodate a very broad range of turbo code block sizes. It is noted that the QPP interleaving as described herein can be applied to turbo encoding and turbo decoding (e.g., including both interleaving and de-interleaving).

    摘要翻译: 二次多项式置换(QPP)交织器,提供适用于任何可能的turbo码块大小的硬件保存和灵活的粒度。 提出了一种手段,其中仅需要非常少量的系数来存储多个QPP交织,以便可以在turbo编码的上下文中使用。 在一种情况下,为了适应3GPP LTE信道编码中的大约6000个不同的Turbo码块大小,仅需要存储5个不同的系数值,以实现要应用那些各种turbo码块大小中的每一个的非常宽范围的QPP交织。 此外,需要采用少量的虚拟位(如果有的话)以适应非常宽范围的turbo码块大小。 注意,如本文所述的QPP交织可以应用于turbo编码和turbo解码(例如,包括交织和解交织两者)。

    General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes
    76.
    发明申请
    General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes 有权
    通用和代数构造的无争用内存映射,用于并行turbo解码,具有所有可能尺寸的代数交错ARP(几乎规则排列)

    公开(公告)号:US20080086673A1

    公开(公告)日:2008-04-10

    申请号:US11704068

    申请日:2007-02-08

    IPC分类号: H03M13/00

    摘要: General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes. A novel means is presented in which contention-free memory mapping is truly achieved in the context of performing parallel decoding of a turbo coded signal. A novel means of performing the contention-free memory mapping is provided to ensure that any one turbo decoder (of a group of parallel arranged turbo decoders) accesses only memory (of a group of parallel arranged memories) at any given time. In doing so, access conflicts between the turbo decoders and the memories are avoided.

    摘要翻译: 通用和代数构造的无竞争存储器映射,用于具有所有可能大小的代数交织ARP(几乎规则排列)的并行turbo解码。 提出了一种新颖的手段,其中在执行turbo编码信号的并行解码的上下文中真正地实现了无竞争存储器映射。 提供执行无竞争存储器映射的新颖方式,以确保任何一个turbo解码器(一组并行布置的turbo解码器)在任何给定时间仅访问存储器(一组并行布置的存储器)。 在这样做时,避免turbo解码器和存储器之间的访问冲突。

    LDPC (low density parity check) coded modulation hybrid decoding
    78.
    发明申请
    LDPC (low density parity check) coded modulation hybrid decoding 有权
    LDPC(低密度奇偶校验)编码调制混合解码

    公开(公告)号:US20080005650A1

    公开(公告)日:2008-01-03

    申请号:US11701156

    申请日:2007-02-01

    IPC分类号: G06F11/00

    摘要: LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until a sufficient degree of precision is achieved. The symbol node updating of the bit edge messages involves using symbol metrics corresponding to the symbol being decoded as well as the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages involves using the bit edge messages most recently updated by symbol node updating. The symbol node updating also involves computing possible soft symbol estimates for the symbol during each decoding iteration.

    摘要翻译: LDPC(低密度奇偶校验)编码调制混合解码。 提出了一种新颖的方法,其中对LDPC编码信号执行比特解码和符号级解码(例如混合解码)的组合。 对于预定数量的解码迭代,或直到达到足够的精确度,连续替代地对位边消息执行检查节点更新和符号节点更新。 位边消息的符号节点更新涉及使用与被解码的符号相对应的符号度量以及最近由校验节点更新更新的位边消息。 位边消息的校验节点更新涉及使用最近通过符号节点更新更新的位边消息。 符号节点更新还涉及在每次解码迭代期间计算符号的可能的软符号估计。

    8 PSK rotationally invariant turbo trellis coded modulation without parallel transitions
    79.
    发明授权
    8 PSK rotationally invariant turbo trellis coded modulation without parallel transitions 有权
    8个PSK旋转不变的turbo网格编码调制,没有并行转换

    公开(公告)号:US07239667B2

    公开(公告)日:2007-07-03

    申请号:US10407012

    申请日:2003-04-03

    IPC分类号: H04L5/12

    摘要: 8 PSK (Phase Shift Keying) rotationally invariant turbo trellis coded modulation without parallel transitions. A novel approach of coding 8 PSK symbols such that they are rotationally invariant employs precoding and encoding according to Turbo Trellis Coded Modulation (TTCM). Together, the preceding and TTCM encoding operate cooperatively to provide rotational invariance of the 8 PSK symbols. These 8 PSK symbols are mapped to constellation points within an 8 PSK constellation. A permutated mapping of the 8 PSK constellation is also employed that describes an approximate 90 degree rotation of the 8 PSK constellation mapping. In addition, the precoding employs an induced precoder mapping that corresponds to the approximate 90 degree rotation of the mapping of the 8 PSK constellation. Moreover, the branches of the trellis employed within the TTCM encoding may undergo an appropriately modified mapping to accommodate the 90 degree rotation of the 8 PSK constellation mapping as well.

    摘要翻译: 8 PSK(相移键控)旋转不变的turbo网格编码调制,无需并行转换。 编码8个PSK符号使得它们是旋转不变性的新颖方法使用根据Turbo网格编码调制(TTCM)的预编码和编码。 一起,前述和TTCM编码协同工作以提供8个PSK符号的旋转不变性。 这8个PSK符号映射到8 PSK星座内的星座点。 也采用了8 PSK星座的置换映射,描述了8 PSK星座映射的近似90度旋转。 另外,预编码采用对应于8 PSK星座的映射的大约90度旋转的感应预编码器映射。 此外,在TTCM编码中采用的网格的分支也可以进行适当修改的映射,以适应8 PSK星座映射的90度旋转。

    LDPC (low density parity check) coded modulation hybrid decoding
    80.
    发明授权
    LDPC (low density parity check) coded modulation hybrid decoding 有权
    LDPC(低密度奇偶校验)编码调制混合解码

    公开(公告)号:US07185270B2

    公开(公告)日:2007-02-27

    申请号:US10723574

    申请日:2003-11-26

    IPC分类号: G06F11/00 H03M13/00

    摘要: LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until a sufficient degree of precision is achieved. The symbol node updating of the bit edge messages involves using symbol metrics corresponding to the symbol being decoded as well as the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages involves using the bit edge messages most recently updated by symbol node updating. The symbol node updating also involves computing possible soft symbol estimates for the symbol during each decoding iteration.

    摘要翻译: LDPC(低密度奇偶校验)编码调制混合解码。 提出了一种新颖的方法,其中对LDPC编码信号执行比特解码和符号级解码(例如混合解码)的组合。 对于预定数量的解码迭代,或直到达到足够的精确度,连续替代地对位边消息执行检查节点更新和符号节点更新。 位边消息的符号节点更新涉及使用与被解码的符号相对应的符号度量以及最近由校验节点更新更新的位边消息。 位边消息的校验节点更新涉及使用最近通过符号节点更新更新的位边消息。 符号节点更新还涉及在每次解码迭代期间计算符号的可能的软符号估计。