公开(公告)号：US20170187394A1

公开(公告)日：2017-06-29

申请号：US15423539

申请日：2017-02-02

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

IPC: H03M13/27 ,  H04L1/00 ,  H03M13/11

CPC classification number: H03M13/2792 ,  H03M13/1148 ,  H03M13/116 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/2778 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/0071

Abstract: A bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

公开(公告)号：US09680505B2

公开(公告)日：2017-06-13

申请号：US14715845

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong-sil Jeong ,  Kyung-joong Kim ,  Se-ho Myung

IPC: H03M13/00 ,  H03M13/27 ,  H04L1/00 ,  H03M13/11

CPC classification number: H03M13/2792 ,  H03M13/1148 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/271 ,  H03M13/2732 ,  H03M13/2778 ,  H03M13/2906 ,  H03M13/616 ,  H03M13/6519 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0071

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.

公开(公告)号：US20170163290A1

公开(公告)日：2017-06-08

申请号：US15435042

申请日：2017-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-joong KIM ,  Se-ho MYUNG ,  Hong-sil JEONG ,  Daniel Ansorregui LOBETE ,  Belkacem MOUHOUCHE

IPC: H03M13/11 ,  H03M13/00 ,  H04L1/00 ,  H03M13/27

CPC classification number: H03M13/2792 ,  H03M13/1102 ,  H03M13/1165 ,  H03M13/255 ,  H03M13/271 ,  H03M13/356 ,  H03M13/6538 ,  H03M13/6552 ,  H03M13/6555 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0071

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

公开(公告)号：US20170155473A1

公开(公告)日：2017-06-01

申请号：US15432078

申请日：2017-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong-sil JEONG ,  Kyung-joong KIM ,  Se-ho MYUNG ,  Daniel Ansorregui LOBETE ,  Belkacem MOUHOUCHE

IPC: H04L1/00 ,  H03M13/00 ,  H03M13/27 ,  H04L27/36 ,  H03M13/11

CPC classification number: H04L1/0041 ,  G06F11/1004 ,  H03M13/1102 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/253 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/2778 ,  H03M13/2792 ,  H03M13/616 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0071 ,  H04L27/36

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

公开(公告)号：US20170149455A1

公开(公告)日：2017-05-25

申请号：US15425734

申请日：2017-02-06

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Bo-Mi LIM ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

IPC: H03M13/27 ,  H03M13/00 ,  H04L1/00 ,  H03M13/11

CPC classification number: H03M13/2792 ,  G06F11/1076 ,  H03M13/1102 ,  H03M13/1148 ,  H03M13/116 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/2778 ,  H03M13/616 ,  H03M13/6552 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/0071

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

公开(公告)号：US20170149453A1

公开(公告)日：2017-05-25

申请号：US15423496

申请日：2017-02-02

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

IPC: H03M13/27 ,  H03M13/11 ,  H03M13/00 ,  H04L1/00

CPC classification number: H03M13/2792 ,  H03M13/036 ,  H03M13/1148 ,  H03M13/116 ,  H03M13/1165 ,  H03M13/255 ,  H03M13/616 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/0071

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

公开(公告)号：US20170149450A1

公开(公告)日：2017-05-25

申请号：US15427623

申请日：2017-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong-sil JEONG ,  Kyung-joong KIM ,  Se-ho MYUNG

IPC: H03M13/11 ,  H03M13/27 ,  H03M13/00 ,  H04L1/00

CPC classification number: H03M13/2792 ,  H03M13/1148 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/271 ,  H03M13/2732 ,  H03M13/2778 ,  H03M13/2906 ,  H03M13/616 ,  H03M13/6519 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0071

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.

公开(公告)号：US20170134046A1

公开(公告)日：2017-05-11

申请号：US15412991

申请日：2017-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se-ho MYUNG ,  Belkacem MOUHOUCHE ,  Daniel Ansorregui LOBETE ,  Kyung-joong KIM ,  Hong-sil JEONG

IPC: H03M13/11 ,  H04L1/00 ,  H03M13/00 ,  H04J13/00 ,  H04J13/12

CPC classification number: H03M13/1105 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/253 ,  H03M13/255 ,  H03M13/271 ,  H03M13/2778 ,  H03M13/611 ,  H03M13/6552 ,  H04J13/0003 ,  H04J13/12 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0065 ,  H04L1/0071

Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

公开(公告)号：US20170118061A1

公开(公告)日：2017-04-27

申请号：US15190594

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Adrian P. Stephens ,  John S. Sadowsky

IPC: H04L27/34 ,  H04L5/00

CPC classification number: H04L27/345 ,  H03M13/255 ,  H04L5/0007 ,  H04L5/0044 ,  H04L27/20 ,  H04L27/2602 ,  H04L27/2627 ,  H04L27/2649 ,  H04W84/12

Abstract: Methods and systems for communicating in a wireless network may distinguish different types of packet structures by modifying the phase of a modulation constellation, such as a binary phase shift keying (BPSK) constellation, in a signal field. Receiving devices may identify the type of packet structure associated with a transmission or whether the signal field is present by the phase of the modulation constellation used for mapping for the signal field. In one embodiment, the phase of the modulation constellation may be determined by examining the energy of the I and Q components after Fast Fourier Transform. Various specific embodiments and variations are also disclosed.

公开(公告)号：US20170117923A1

公开(公告)日：2017-04-27

申请号：US15402107

申请日：2017-01-09

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM ,  Nam-Ho HUR

IPC: H03M13/27 ,  H03M13/11 ,  H03M13/00 ,  H04L1/00

CPC classification number: H03M13/2792 ,  H03M13/1102 ,  H03M13/116 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/2757 ,  H03M13/2778 ,  H03M13/616 ,  H03M13/6552 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0058 ,  H04L1/0071 ,  H04L27/20 ,  H04L27/3416

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.