公开(公告)号：US11508725B2

公开(公告)日：2022-11-22

申请号：US16777639

申请日：2020-01-30

申请人： QUALCOMM Incorporated

发明人： Seid Hadi Rasouli ,  Michael Joseph Brunolli ,  Christine Sung-An Hau-Riege ,  Mickael Malabry ,  Sucheta Kumar Harish ,  Prathiba Balasubramanian ,  Kamesh Medisetti ,  Nikolay Bomshtein ,  Animesh Datta ,  Ohsang Kwon

IPC分类号： H01L27/092 ,  H01L23/482 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8238 ,  H01L23/522 ,  H03K17/16 ,  H03K17/687

摘要： A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

公开(公告)号：US11502678B2

公开(公告)日：2022-11-15

申请号：US17527037

申请日：2021-11-15

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Zijiang Yang ,  Nuttapong Srirattana

IPC分类号： H03K17/16 ,  H01L27/12 ,  H04B1/40

摘要： Radio-frequency switch having improved linearity. In some embodiments, a radio-frequency switch circuit can include first and second switch arms, with each switch arm including a plurality of transistors arranged in series to form a stack between a first node and a second node. The first node of the first switch arm can be coupled to the first node of the second switch arm. The radio-frequency switch circuit can further include an amplitude-phase cancelling block implemented across one or more transistors of each switch arm, and configured such that a third harmonic resulting from an ON state of the first switch arm is substantially canceled by a third harmonic resulting from an OFF state of the second switch arm.

公开(公告)号：US11469756B2

公开(公告)日：2022-10-11

申请号：US16863845

申请日：2020-04-30

申请人： Power Integrations, Inc.

发明人： Jan Thalheim

IPC分类号： H03K17/56 ,  H03K17/082 ,  H03K17/16 ,  H02H3/08

摘要： A turn-off circuit for a semiconductor switch includes an element having a variable resistance coupled to a control input of the semiconductor switch, a circuit for generating a control-input reference signal, and a control circuit coupled to adjust a resistance of the element having a variable resistance in response to the control-input reference signal in a closed control loop in order to turn off the semiconductor switch.

公开(公告)号：US11469755B2

公开(公告)日：2022-10-11

申请号：US17425604

申请日：2020-01-21

申请人： Agency for Science, Technology and Research

发明人： Yong-Joon Jeon

IPC分类号： H03K17/00 ,  H03K17/284 ,  H03K17/06 ,  H03K17/16

摘要： This document discloses a comparator that is configured to control dead-time between two or more switching transistors. In particular, it is disclosed that the comparator is configured to generate a suitable delay between the switching “OFF” of a transistor and the switching “ON” of another transistor so that the amount of shoot through current flowing between these two transistors are greatly minimized.

公开(公告)号：US20220311432A1

公开(公告)日：2022-09-29

申请号：US17839386

申请日：2022-06-13

申请人： pSemi Corporation

发明人： Christopher N. Brindle ,  Michael A. Stuber ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George Imthurn ,  Robert B. Welstand ,  Mark L. Burgener

IPC分类号： H03K17/16 ,  H01L29/786 ,  H01L29/06 ,  H01L29/10 ,  H03K17/687

摘要： A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FIT performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

公开(公告)号：US20220278679A1

公开(公告)日：2022-09-01

申请号：US17625695

申请日：2020-06-04

申请人： Robert Bosch GmbH

发明人： Alexander Kaiser ,  Moritz Schollbach ,  Peter Sinn ,  Tobias Richter

IPC分类号： H03K17/16 ,  H03K17/18 ,  H03K17/0412

摘要： The invention relates to a circuit arrangement (100), comprising a control circuit (104) and a switch element (101) for switching between a first and a second switching state of the switch element (101). The control circuit (104) is designed to provide a variable pre-control voltage dependent on the switching state of the switch element. The pre-control voltage is a voltage that is switched as the control voltage at the switch element (101) during one of the two switching states. The control circuit (104) is also designed to vary the pre-control voltage during each of the switching states.

公开(公告)号：US11431331B2

公开(公告)日：2022-08-30

申请号：US16967856

申请日：2019-02-06

申请人： GENERAL ELECTRIC TECHNOLOGY GMBH

发明人： John Lewis Outram

IPC分类号： H03K17/0812 ,  H03K17/16

摘要： A switching apparatus (20) comprises first and second current paths, each current path configured to be capable of conducting an electrical current, the first current path including a first switching element (28) connected in parallel with a first passive current check element (30), the switching apparatus (20) further including a switching controller configured to selectively control the switching of the first switching element (28), wherein the switching controller is configured to selectively switch the first switching element (28) at a first intra-current path switching speed to commutate the electrical current between the first switching element (30) and the first passive current check element (32), the switching controller is configured to selectively switch the first switching element (28) at a first inter-current path switching speed to commutate the electrical current between the first and second current paths, and the first intra-current path switching speed is faster or slower than the first inter-current path switching speed.

公开(公告)号：US11424670B2

公开(公告)日：2022-08-23

申请号：US17188284

申请日：2021-03-01

申请人： DENSO CORPORATION

发明人： Koichi Nishibata

IPC分类号： H02M1/08 ,  H02M3/158 ,  H02M7/5387 ,  H03K17/16 ,  H02M1/00 ,  H02P27/08

摘要： A drive device performs switching of at least one switch configuring an electrical power converter. The drive device includes a control section that generates a drive signal for the switch and transmits the drive signal, and at least one drive circuit that receives the transmitted drive signal. The control section generates speed adjustment information for adjusting a switching speed of the switch and transmits the speed adjustment information to the drive circuit. The drive circuit includes a speed calculation section that receives the transmitted speed adjustment information and calculates command switching speed information of the switch based on the received speed adjustment information, and a drive section that performs switching of the switch based on the received drive signal and the calculated command switching speed information.

公开(公告)号：US20220263500A1

公开(公告)日：2022-08-18

申请号：US17734227

申请日：2022-05-02

申请人： Texas Instruments Incorporated

发明人： Abhijit Kumar Das ,  Ryan Alexander Smith

IPC分类号： H03K5/1252 ,  H03K17/16

摘要： One example includes a glitch filter system. The system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.

公开(公告)号：US11418186B2

公开(公告)日：2022-08-16

申请号：US17244162

申请日：2021-04-29

申请人： pSemi Corporation

发明人： Ethan Prevost ,  Michael Conry

IPC分类号： H03K17/16 ,  H04B1/04 ,  H03K17/00

摘要： An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in a low loss mode, in a bypass mode, or, optionally, in a signal function mode. Embodiments of the invention allow for both a single switch in the series input path to a target circuit while still having the ability to isolate the bypass path from the target circuit. In the low loss and bypass mode, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.