公开(公告)号：US07017064B2

公开(公告)日：2006-03-21

申请号：US09851169

申请日：2001-05-09

申请人： Terence Neil Thomas ,  Stephen J. Davis

发明人： Terence Neil Thomas ,  Stephen J. Davis

IPC分类号： G06F1/12

CPC分类号： G06F7/728 ,  G06F1/10 ,  G06F7/00 ,  G06F2207/3884

摘要： A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

公开(公告)号：US07003625B2

公开(公告)日：2006-02-21

申请号：US10386378

申请日：2003-03-10

申请人： Lawrence King

发明人： Lawrence King

IPC分类号： G06F12/00

CPC分类号： H04L45/00 ,  G11C15/00 ,  H04L45/7453

摘要： A plurality of entities are stored in a single addressable location in a Content Addressable Memory (CAM). A column in a CAM entry is selected for storing an entity based on the property of the entity to distribute the entities among the columns to maximize memory utilization. A match for a search key stored in one of the plurality of columns can be found in a single search operation.

摘要翻译： 多个实体存储在内容可寻址存储器（CAM）中的单个可寻址位置中。 选择CAM条目中的列以基于实体的属性存储实体以在列之间分布实体以最大化内存利用率。 可以在单个搜索操作中找到存储在多个列之一中的搜索关键字的匹配。

公开(公告)号：US07002824B2

公开(公告)日：2006-02-21

申请号：US10912768

申请日：2004-08-05

申请人： Robert N. McKenzie ,  Dieter Haerle ,  Sean Lord

发明人： Robert N. McKenzie ,  Dieter Haerle ,  Sean Lord

IPC分类号： G11C15/00

CPC分类号： G11C15/043 ,  G11C15/00 ,  G11C15/04

摘要： A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The search result for the CAM is selected based on the propagated search results for each row of sub-blocks and output on a side of the array opposite from the side receiving the search data.

公开(公告)号：US20050175005A1

公开(公告)日：2005-08-11

申请号：US11099724

申请日：2005-04-06

申请人： David Brown

发明人： David Brown

IPC分类号： G06F12/10 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L45/00 ,  H04L45/7457

摘要： A lookup unit matrix combines a plurality of lookup units to provide a longest prefix match for a search key longer than the lookup unit's mapper key. A portion of the search key is provided to each of the plurality of lookup units in a single search request issued to the lookup unit matrix. Each lookup unit in the lookup unit matrix performs a multi-level search for the result value based on the portion of the search key forwarded as the mapper key and the result of a multilevel search in the previous lookup unit. The search results in a value corresponding to the search key stored in a single location in one of the lookup units.

摘要翻译： 查找单元矩阵组合多个查找单元以提供比查找单元的映射关键字长的搜索关键字的最长前缀匹配。 在发布给查找单元矩阵的单个搜索请求中，将搜索关键字的一部分提供给多个查找单元中的每一个。 查找单元矩阵中的每个查找单元基于作为映射器键转发的搜索关键字的部分和在先前查找单元中的多级搜索的结果来执行结果值的多级搜索。 该搜索产生与存储在一个查找单元中的单个位置的搜索关键字对应的值。

公开(公告)号：US06917954B2

公开(公告)日：2005-07-12

申请号：US10132675

申请日：2002-04-24

申请人： Imtiaz Ahmad ,  David A. Brown

发明人： Imtiaz Ahmad ,  David A. Brown

IPC分类号： G06F7/00 ,  G06F17/00 ,  G06F17/30 ,  H04L12/00 ,  H04L12/56

CPC分类号： H04L45/745 ,  Y10S707/99933 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99956

摘要： A load balancing mechanism maps a binary tree representation of a routing table into a set of fixed size memories. The mechanism efficiently utilizes the memory in the routing table without violating the tree precedence constraints and the memory access requirements of a pipelined system. The mechanism stores a subtree associated with a densely populated level of the binary tree in memory associated with lower levels.

摘要翻译： 负载平衡机制将路由表的二叉树表示映射到一组固定大小的存储器中。 该机制有效地利用路由表中的存储器，而不违反流优先级约束和流水线系统的存储器访问要求。 该机制将与二进制树的密集层次相关联的子树存储在与较低级别相关联的存储器中。

公开(公告)号：US06879271B2

公开(公告)日：2005-04-12

申请号：US10788003

申请日：2004-02-27

申请人： Mourad Abdat

发明人： Mourad Abdat

IPC分类号： H03M7/42 ,  H03M7/30

CPC分类号： H03M7/3088

摘要： We present a method and apparatus for performing adaptive data compression. An alphabet and vocabulary in the encoder and decoder is built adaptively and stored in a dictionary as symbols are to be encoded and decoded. Each time an unknown symbol is to be encoded by the encoder, the encoder adds the symbol to the dictionary and transmits it in plain in the encoded string. The code words transmitted by the encoder include symbols and indexes. The state of a prefix bit preceding the code word indicates whether the code word is a plain symbol or an index of a symbol or string of symbols stored in the dictionary. The decoder examines the prefix bit of each code word as it is received to determine if the code word stores a symbol in plain or in index. If the code word stores a symbol in plain, the decoder learns the symbol by adding a sequence of symbols resulting from the concatenation of previously decoded symbols and the first symbol of the currently decoded symbol and by adding the symbol to its dictionary. If the code word stores an index, the decoder decodes the code word by extracting the symbol or sequence of symbols stored in the dictionary at the respective index in the dictionary.

摘要翻译： 我们提出一种执行自适应数据压缩的方法和装置。 编码器和解码器中的字母和词汇表被自适应地构建并存储在字典中，因为符号将被编码和解码。 每当编码器对未知符号进行编码时，编码器将符号添加到字典中，并以编码字符串的形式将其传输。 由编码器发送的码字包括符号和索引。 代码字之前的前缀位的状态指示代码字是否是存储在字典中的符号或符号串的简单符号或索引。 解码器检查每个代码字的前缀位，因为它被接收以确定代码字是否以简单或索引存储符号。 如果代码字平原存储符号，则解码器通过将从先前解码的符号的连接和当前解码的符号的第一符号产生的符号序列并通过将符号添加到其字典来学习符号。 如果码字存储索引，则解码器通过在字典中的相应索引处提取存储在字典中的符号或符号序列来解码码字。

公开(公告)号：US06862287B2

公开(公告)日：2005-03-01

申请号：US10187472

申请日：2002-06-28

申请人： David A. Brown

发明人： David A. Brown

IPC分类号： H04L12/56

CPC分类号： H04L45/00 ,  H04L45/745

摘要： A number of hash tables are accessed concurrently with a different computed index based on a single search key for each hash table. Each index identifies a location in one of the hash tables capable of storing at least one entry. If all indexed locations are used, the entries stored in the lookup table can be reordered so that the new entry can be inserted in one of the locations identified by the computed indexes.

摘要翻译： 基于每个哈希表的单个搜索关键字，使用不同的计算索引同时访问多个哈希表。 每个索引标识能够存储至少一个条目的哈希表之一的位置。 如果使用所有索引位置，则可以重新排序存储在查找表中的条目，以便可以将新条目插入由计算的索引标识的一个位置中。

公开(公告)号：US06839825B1

公开(公告)日：2005-01-04

申请号：US09886649

申请日：2001-06-21

申请人： David A. Brown

发明人： David A. Brown

IPC分类号： G06F12/00

CPC分类号： G06F12/0292 ,  G06F12/04 ,  G06F2212/1044

摘要： A method and apparatus for minimizing memory required for storing non-binary width data structures is disclosed. The non-binary width data structure is segmented into plural segments. The segments are stored in a plurality of memory blocks. Mapper logic maps a logical address to a physical address in the memory blocks to access non-binary width entries in the non-binary width data structure stored in the memory blocks.

摘要翻译： 公开了一种用于最小化存储非二进制宽度数据结构所需的存储器的方法和装置。 非二进制宽度数据结构被分割成多个段。 这些段被存储在多个存储块中。 映射器逻辑将逻辑地址映射到存储器块中的物理地址，以访问存储在存储器块中的非二进制宽度数据结构中的非二进制宽度条目。

公开(公告)号：US20040264621A1

公开(公告)日：2004-12-30

申请号：US10647664

申请日：2003-08-25

申请人： MOSAID Technologies, Inc.

发明人： Tony Mai

IPC分类号： H03D003/24

CPC分类号： H03L7/10 ,  H03L7/0812 ,  H03L7/0891

摘要： An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.

摘要翻译： 延迟锁定环路中的初始化电路确保上电或其他复位时钟沿由相位检测器以适当的顺序以适当的顺序接收。 在延迟锁定环路复位之后，初始化电路确保在使相位检测器增加（或减小）延迟线中的延迟之前，接收到参考时钟的至少一个边沿。 在接收到反馈时钟的至少一个边缘之后，初始化电路使相位检测器能够减小（或增加）延迟线中的延迟。

公开(公告)号：US20030179012A1

公开(公告)日：2003-09-25

申请号：US10395318

申请日：2003-03-21

申请人： MOSAID Technologies, Inc.

发明人： Raymond Jit-Hung Sung ,  John Conrad Koob ,  Tyler Lee Brandon ,  Duncan George Elliot

IPC分类号： H03K019/094

CPC分类号： H04L5/1461

摘要： A circuit and method for accelerating bus line communication in an integrated circuit is disclosed. High speed transmission of signals along a bus line is achieved by driving a series of bus line segments with their own bi-directional bus amplification circuits. Because each bus line segment has less capacitive loading than longer non-segmented bus lines, voltage reversal, or data inversion of a pair of complementary lines of a bus line segment is accomplished at high speed. Each bi-directional bus amplification circuit includes a precharge circuit for precharging each complementary pair of lines to known logic levels, and a drive circuit for changing the logic level of each line. The bi-directional bus amplification circuit of the present invention logically connects two lines to each other while actively amplifying the signal in either direction without prior knowledge of which direction the signal must be driven, and without additional control overhead than that required for a conventional precharged bus line.

摘要翻译： 公开了一种用于加速集成电路中的总线通信的电路和方法。 通过用自己的双向总线放大电路驱动一系列总线线段，实现沿总线线路的信号的高速传输。 因为每个总线段具有比较长的非分段总线线路更少的电容负载，所以高速地实现总线线段的一对互补线的电压反转或数据反转。 每个双向总线放大电路包括预充电电路，用于将每条互补线对预充电到已知逻辑电平，以及用于改变每条线的逻辑电平的驱动电路。 本发明的双向总线放大电路逻辑上将两条线彼此逻辑地连接，同时在任一方向上主动放大信号，而不需要先前知道信号必须被驱动的方向，而不需要额外的控制开销，而不需要常规的预充电 公车线。