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    APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY
    6.
    发明申请
    APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY 审中-公开

    公开(公告)号：US20170309314A1

    公开(公告)日：2017-10-26

    申请号：US15133986

    申请日：2016-04-20

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Sanjay Tiwari

    IPC: G11C7/06 ,  G11C8/16 ,  G11C8/10

    CPC classification number: G11C7/065 ,  G11C8/10 ,  G11C8/16 ,  G11C15/043

    Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

    APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY
    8.
    发明申请
    APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY 有权
    使用感应电路执行比较操作的装置和方法

    公开(公告)号：US20170025160A1

    公开(公告)日：2017-01-26

    申请号：US15287980

    申请日：2016-10-07

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

    Abstract translation: 本公开包括与使用感测电路执行比较和/或报告操作相关的装置和方法。 示例性方法可以包括将存储器阵列的输入/输出（IO）线充电到电压。 该方法可以包括确定存储在存储器阵列中的数据是否与比较值相匹配。 确定存储的数据是否与比较值匹配可以包括激活存储器阵列的多个访问线。 该确定可以包括感测耦合到接入线路数量的多个存储器单元。 该确定可以包括检测IO线的电压是否响应于对应于存储器单元的数量的所选择的解码线的激活而改变。

    Charge sharing in a TCAM array
    10.
    发明授权
    Charge sharing in a TCAM array 有权
    TCAM阵列中的电荷共享

    公开(公告)号：US09076527B2

    公开(公告)日：2015-07-07

    申请号：US13233065

    申请日：2011-09-15

    Applicant: Oren Agam ,  Avidan Akerib ,  Eli Ehrman ,  Moshe Meyassed

    Inventor： Oren Agam ,  Avidan Akerib ,  Eli Ehrman ,  Moshe Meyassed

    IPC: G11C15/00 ,  G11C15/04 ,  G11C8/08 ,  G11C8/10 ,  G11C7/10 ,  G11C11/403

    CPC classification number: G11C15/043 ,  G11C7/1006 ,  G11C8/08 ,  G11C8/10 ,  G11C11/403

    Abstract: A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.

    Abstract translation: 存储单元包括存储电容器，读取线路和存储晶体管，其中存储晶体管连接到读取线并且通过存储电容器中的电荷进行激活。 存储器内存处理器包括存储数据的存储器阵列和激活单元，用于在大致相同的时间激活存储器阵列的列中的至少两个单元，从而生成至少该数据的布尔函数输出 两个单元，其中所述至少两个单元中的每一个至少包括存储电容器，存储晶体管和读取线，其中所述存储晶体管连接到所述读取线并通过所述存储电容器中的电荷进行激活。

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